# US 12,183,682 B2 · Semiconductor package and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,682 B2 - Document ID: US12183682B2 - Status: Granted - Kind: B2 - Application number: 17/371,110 - Filed: 2021-07-09 - Published: 2023-01-12 - Granted: 2024-12-31 - Earliest claimed: 2021-07-09 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chien-Hsun Chen; Chien-Hsun Lee; Chung-Shi Liu; Jiun-Yi Wu; Shou-Yi Wang; Tsung-Ding Wang - Web page: https://patentgrep.com/patent/US12183682B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/00: Interconnections or connectors in packages - H10P 72/74: {using temporarily an auxiliary support} - H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes} - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/7416: {used during dicing or grinding} - H10P 72/7422: {used to protect an active side of a device or wafer} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/635: {Through-vias} - H10W 72/227: {Multiple bumps having different sizes} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/473: {containing a filler} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region. ## Claims ### Claim 1 A semiconductor package, comprising: semiconductor dies, laterally spaced apart from one another, and comprising die inputs/outputs (I/Os) at active sides of the semiconductor dies; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure comprises a first routing layer and a second routing layer sequentially arranged along a direction away from the die I/Os, wherein the first routing layer comprises a first ground plane and first signal lines, the first signal lines are located at where the first ground plane is discontinuous, the first signal lines respectively have two pad portions and a line portion extending between the two pad portions, one of the two pad portions of each first signal line is located within a central region of the redistribution structure, the other pad portion of each first signal line is located within a peripheral region of the redistribution structure, and wherein the second routing layer comprises second signal lines and first ground lines, the second signal lines are electrically connected to the first signal lines, the first ground lines are electrically connected to the first ground plane, the second signal lines and the first ground lines respectively have two pad portions and a line portion extending in between, the two pad portions of each of the second signal lines and the first ground lines are both located in the peripheral region of the redistribution structure, and the line portion of each of the second signal lines and the first ground lines passes through the central region of the redistribution structure. ### Claim 2 (depends on 1) The semiconductor package according to claim 1, wherein the pad portions of the first signal lines within the central region of the redistribution structure are positioned in correspondence to the die I/Os of the semiconductor dies. ### Claim 3 (depends on 1) The semiconductor package according to claim 1, wherein the first signal lines are laterally surrounded by the first ground plane, and are isolated from the first ground plane. ### Claim 4 (depends on 1) The semiconductor package according to claim 1, wherein each of the first ground lines is arranged between two of the second signal lines. ### Claim 5 (depends on 1) The semiconductor package according to claim 1, wherein the line portions of the second signal lines are parallel with the line portions of the first ground lines. ### Claim 6 (depends on 1) The semiconductor package according to claim 1, wherein an interconnection between adjacent ones of the semiconductor dies is established though the second signal lines. ### Claim 7 (depends on 1) The semiconductor package according to claim 1, wherein the second signal lines and the first ground lines are overlapped with the first ground plane. ### Claim 8 (depends on 1) The semiconductor package according to claim 1, wherein the redistribution structure further comprises a third routing layer more distant from the die I/Os than the first and second routing layers, the third routing layer comprises third signal lines and second ground lines, each of the third signal lines and the second ground lines has two pad portions and a line portion extending in between, the two pad portions of each of the third signal lines and the second ground lines are located within the peripheral region, and the line portion of each of the third signal lines and the second ground lines passes through the central region. ### Claim 9 (depends on 8) The semiconductor package according to claim 8, wherein each of the second signal lines is overlapped with the first ground plane and one of the second ground lines, and is arranged between adjacent ones of the first ground lines. ### Claim 10 (depends on 8) The semiconductor package according to claim 8, wherein the redistribution structure further comprises a fourth routing layer more distant from the die I/Os than the first, second and third routing layers, the fourth routing layer comprises a second ground plane and a power plane laterally surrounded by the second ground plane and isolated from the second ground plane. ### Claim 11 (depends on 10) The semiconductor package according to claim 10, wherein each of the third signal lines is overlapped with one of the first ground lines and the second ground plane, and is arranged between adjacent ones of the second ground lines. ### Claim 12 (depends on 1) The semiconductor package according to claim 1, further comprises an encapsulant laterally encapsulating the semiconductor dies, and in contact with the redistribution structure. ### Claim 13 (depends on 1) The semiconductor package according to claim 1, wherein the die I/Os are conductive pillars, and the redistribution structure comprises a stack of polymer layers in which the first and second routing layers are formed. ### Claim 14 A semiconductor package, comprising: semiconductor dies, laterally spaced apart from one another, and comprising die inputs/outputs (I/Os) at active sides of the semiconductor dies; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure comprises a first routing layer and a second routing layer sequentially arranged along a direction away from the die I/Os, wherein the first routing layer comprises a ground plane and first signal lines, the first signal lines are laterally surrounded by and isolated from the first ground plane, a first terminal of each first signal line is positioned in correspondence with one of the die I/Os and located within a central region of the redistribution structure, and the first signal lines extending from the first terminals are bounded at second terminals arranged along a same lateral side of the redistribution structure, and wherein the second routing layer comprises second signal lines and ground lines each having two terminals arranged along the lateral side of the redistribution structure, the second signal lines each extend from the second terminal of one of the first signal lines to the second terminal of another one of the first signal lines through the central region of the redistribution structure, and the ground lines each extend between adjacent ones of the second signal lines. ### Claim 15 (depends on 14) The semiconductor package according to claim 14, further comprising electrical connectors, disposed at a surface of the redistribution structure facing away from the semiconductor dies. ### Claim 16 (depends on 15) The semiconductor package according to claim 15, further comprising a package substrate, on which the electrical connectors are attached. ### Claim 17 (depends on 16) The semiconductor package according to claim 16, wherein the package substrate is further attached onto a printed circuit board through additional electrical connectors. ### Claim 18 A semiconductor package, comprising: a first semiconductor die and a second semiconductor die, laterally spaced apart from each other and encapsulated by an encapsulant, wherein first die I/Os of the first semiconductor dies and second die I/Os of the second semiconductor die extend to a front side of the encapsulant; a first routing layer, disposed at the front side of the encapsulant, and comprising a first ground plane and first signal lines extending in openings defined in the first ground plane, wherein the first signal lines extend from first terminals respectively positioned in correspondence with one of the first and second die I/Os and located within a central region of the first routing layer, and are bounded at second terminals arranged along a same lateral side of the first routing layer; and a second routing layer, disposed at a side of the first routing layer facing away from the encapsulant, and comprising second signal lines and first ground lines extending along and in parallel with the second signal lines, wherein the second signal lines respectively connect the second terminal of one of the first signal lines routed from one of the first die I/Os to the second terminal of another one of the first signal lines routed from one of the second die I/Os, and are each bounded at two terminals arranged along a same lateral side of the second routing layer while passing through a central region of the second routing layer. ### Claim 19 (depends on 18) The semiconductor package according to claim 18, further comprising: a third routing layer, comprising third signal lines and second ground lines extending along and in parallel with the third signal lines, wherein each third signal line establishes a conduction path between one of the first die I/Os and one of the second die I/Os, and all terminals of the third signal lines and the second ground lines are arranged along the same edge of the third routing layer. ### Claim 20 (depends on 19) The semiconductor package according to claim 19, further comprising: a fourth routing layer, comprising a second ground plane formed with an array of openings, and comprising a power plane laterally surrounded by the second ground plane.