# US 12,183,680 B2 · Semiconductor memory device including wiring contact plugs

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- Number: US 12,183,680 B2
- Document ID: US12183680B2
- Status: Granted
- Kind: B2
- Application number: 18/191,418
- Filed: 2023-03-28
- Published: 2023-07-27
- Granted: 2024-12-31
- Earliest claimed: 2020-11-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yonghyeok Son; Junwoo Lee; Sungdong Cho
- Web page: https://patentgrep.com/patent/US12183680B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10B 12/50: {Peripheral circuit region structures}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/0698: {Local interconnections}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

## Claims

### Claim 1

A semiconductor memory device comprising:
a substrate;
a plurality of capacitors including a plurality of lower electrodes on the substrate, an upper electrode on the plurality of lower electrodes, and a plurality of capacitor dielectric layers between the plurality of lower electrodes and the upper electrode; and
a filling insulation layer covering the plurality of capacitors;
wherein the upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers, and a second upper electrode layer on the first upper electrode layer, and
wherein the second upper electrode layer has a stacked structure including an electrode barrier layer and a main electrode layer,
wherein the electrode barrier layer is arranged between the first upper electrode layer and the main electrode layer, and
wherein the first upper electrode layer includes a semiconductor material and the main electrode layer includes a metallic material.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1,
wherein
a thickness of the electrode barrier layer is less than a thickness of the first upper electrode layer and a thickness of the main electrode layer.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, wherein the filling insulation layer includes an ultra-low k (ULK) layer including carbon (C).

### Claim 4 (depends on 3)

The semiconductor memory device of claim 3, wherein the filling insulation layer includes at least one selected from a SiOC layer and a SiCOH layer.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, wherein each of the plurality of lower electrodes is in the form of a pillar extending in a vertical direction.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein each of the plurality of lower electrodes includes titanium nitride.

### Claim 7 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
a plurality of vertical channel transistors between the substrate and the plurality of capacitors,
wherein each of the plurality of vertical channel transistors includes a channel layer extending from the substrate in a vertical direction.

### Claim 8 (depends on 7)

The semiconductor memory device of claim 7, wherein the channel layer includes an oxide semiconductor.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1, wherein
a lower portion of the first upper electrode layer extends towards the substrate into a region between the plurality of lower electrodes.

### Claim 10 (depends on 1)

The semiconductor memory device of claim 1, wherein the second upper electrode layer has a stacked structure further including an interface layer including conductive metal oxide.

### Claim 11

A semiconductor memory device comprising:
a substrate;
a plurality of capacitors including a plurality of lower electrodes on the substrate, a plurality of capacitor dielectric layers conformally covering surfaces of the plurality of lower electrodes, and an upper electrode covering the plurality of capacitor dielectric layers filling spaces among the plurality of lower electrodes, the upper electrode having a stacked structure in which a first electrode layer, an electrode barrier layer, and a second electrode layer are sequentially stacked; and
a filling insulation layer covering the plurality of capacitors, the filling insulation layer includes carbon (C), wherein
the second electrode layer includes a metallic material,
the electrode barrier layer is between the first electrode layer and the second electrode layer, and
the first electrode layer includes a semiconductor material.

### Claim 12 (depends on 11)

The semiconductor memory device of claim 11, wherein
the first electrode layer has a first thickness from uppermost ends of the plurality of capacitor dielectric layers to an upper surface of the first electrode layer,
the second electrode layer has a second thickness from a bottom surface to a top surface of the second electrode layer, and
the first thickness of the first electrode is greater than the second thickness of the second electrode layer.

### Claim 13 (depends on 11)

The semiconductor memory device of claim 11, wherein the upper electrode has a stacked structure further including an interface layer including conductive metal oxide.

### Claim 14 (depends on 11)

The semiconductor memory device of claim 11, further comprising:
an etch stop layer between the upper electrode and the filling insulation layer;
a plurality of wiring lines on the filling insulation layer; and
a wiring contact plug connecting at least one of the plurality of wiring lines to the upper electrode through the filling insulation layer and the etch stop layer,
wherein the wiring contact plug extends to an inside of the second electrode layer through the filling insulation layer and the etch stop layer and has a lower surface at a level higher than an upper surface of the first electrode layer.

### Claim 15 (depends on 11)

The semiconductor memory device of claim 11, wherein each of the plurality of lower electrodes is in the form of a pillar extending in a vertical direction and includes titanium nitride.

### Claim 16 (depends on 11)

The semiconductor memory device of claim 11, further comprising:
a plurality of vertical channel transistors between the substrate and the plurality of capacitors, each of the plurality of vertical channel transistors including a channel layer,
wherein the channel layer includes an oxide semiconductor and extends from the substrate in a vertical direction.

### Claim 17 (depends on 11)

The semiconductor memory device of claim 11, wherein the first electrode layer includes a semiconductor material, and
a lower portion of the first electrode layer extends towards the substrate into a region between the plurality of lower electrodes.

### Claim 18

A semiconductor memory device comprising:
a substrate including a cell area and a peripheral area;
a plurality of gate lines on the peripheral area of the substrate;
a plurality of logic bit lines on the plurality of gate lines;
a plurality of lower electrodes separated from each other on the cell area;
a plurality of capacitor dielectric layers conformally covering the plurality of lower electrodes;
an upper electrode including a first upper electrode layer filling spaces in between the plurality of lower electrodes and covering the plurality of capacitor dielectric layer, an electrode barrier layer covering the first upper electrode layer, and a second upper electrode layer covering the electrode barrier layer such that the electrode barrier layer is between the first upper electrode layer and the second upper electrode layer, the first upper electrode layer including a semiconductor material, and the second upper electrode layer including a metallic material;
an etch stop layer covering the upper electrode;
a filling insulation layer including carbon (C), and covering the etch stop layer,
a plurality of wiring lines on the filling insulation layer;
a first wiring contact plug connecting at least one of the plurality of wiring lines to the upper electrode through the filling insulation layer and the etch stop layer; and
a second wiring contact plug connecting at least another one of the plurality of wiring lines to the plurality of logic bit lines through the filling insulation layer.

### Claim 19 (depends on 18)

The semiconductor memory device of claim 18, wherein a height of the second wiring contact plug is greater than a height of the first wiring contact plug.

### Claim 20 (depends on 18)

The semiconductor memory device of claim 18, wherein the upper electrode includes an interface layer including conductive metal oxide.