# US 12,183,679 B2 · Interconnect structure and electronic apparatus including the same

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- Number: US 12,183,679 B2
- Document ID: US12183679B2
- Status: Granted
- Kind: B2
- Application number: 17/902,319
- Filed: 2022-09-02
- Published: 2022-12-29
- Granted: 2024-12-31
- Earliest claimed: 2019-10-29
- Assignees: Samsung Electronics Co., Ltd.; Unist (Ulsan National Institute of Science and Technology)
- Applicants: Samsung Electronics Co., Ltd.; Unist (Ulsan National Institute of Science and Technology)
- Inventors: Hyeonjin Shin; Minhyun Lee; Changseok Lee; Hyeonsuk Shin; Seokmo Hong
- Web page: https://patentgrep.com/patent/US12183679B2

## CPC

- H10W 20/48: Insulating materials thereof
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4437: {the principal metal being a transition metal}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor layer;
a conductive layer electrically connected to the semiconductor layer; and
a dielectric layer surrounding at least a part of the conductive layer;
wherein the dielectric layer includes an amorphous boron nitride portion and a nanocrystalline boron nitride portion;
the amorphous boron nitride portion includes one or more crystals having a size of about 3 nm or less, and
the nanocrystalline boron nitride portion includes one or more crystals having a size of about 0.5 nm to about 100 nm.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a diffusion barrier layer between the conductive layer and the dielectric layer, the diffusion barrier layer configured to limit a conductive material of the conductive layer from diffusing into the dielectric layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2,
the diffusion barrier layer comprises a material other than boron.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the dielectric layer is about 5 nm or more.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric layer has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric layer has a ratio of boron to nitrogen of about 0.9 to about 1.1.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric layer is non-porous.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric layer comprises at least one pore.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric layer and has a mass density of about 1 to about 3 g/cm3.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein a breakdown field of the dielectric layer and is about 4 MV-cm-1 or more.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric layer has about 0.3 to about 0.6 root-mean-square (RMS) roughness value.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein
the dielectric layer comprises a first dielectric layer comprising a trench of a first depth, and
the conductive layer comprises a first conductive layer filling an inside of the trench.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein
the dielectric layer comprises a second dielectric layer comprising a via hole, and
the conductive layer comprises a second conductive layer filling an inside of the via hole.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the via hole is stepped.

### Claim 15 (depends on 1)

An electronic apparatus comprising:
a device layer comprising at least one of a transistor, a capacitor, and a resistor; and
the semiconductor device of claim 1 connected to the device layer.

### Claim 16 (depends on 15)

The electronic apparatus of claim 15, wherein the device layer comprises at least one of a memory device, a display device, and an integrated circuit device.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric layer has a hydrogen content of about 10% or less and greater than 0%.