# US 12,183,678 B2 · Backside power rail structure and methods of forming same

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- Number: US 12,183,678 B2
- Document ID: US12183678B2
- Status: Granted
- Kind: B2
- Application number: 18/499,481
- Filed: 2023-11-01
- Published: 2024-02-22
- Granted: 2024-12-31
- Earliest claimed: 2019-10-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kuo-Cheng Chiang; Shi Ning Ju; Chih-Chao Chou; Wen-Ting Lan; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12183678B2

## CPC

- H10W 20/427: {Power or ground buses}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10P 50/642: {Chemical etching}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
depositing a first sacrificial layer, a first channel layer, a second sacrificial layer, and a second channel layer sequentially over a semiconductor substrate, wherein a first germanium concentration of the first sacrificial layer is lower than a second germanium concentration of the second sacrificial layer;
replacing the first sacrificial layer with an isolation layer;
forming a first source/drain region and a second source/drain region on opposite sides of the isolation layer, the first channel layer, the second sacrificial layer, and the second channel layer;
replacing the second sacrificial layer with a gate stack, wherein the gate stack is also disposed over a top surface of the second channel layer;
thinning a backside of the semiconductor substrate, wherein after thinning the backside of the semiconductor substrate, a first surface of the isolation layer is level with a second surface of the first source/drain region and a third surface of the second source/drain region; and
forming a backside power rail electrically connected to the first source/drain region, wherein the backside power rail is disposed to be on an opposite side of the isolation layer as the first channel layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the isolation layer comprises a metal oxide.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first germanium concentration is in a range from 1010 atoms/cm3 to 1015 atoms/cm3 and the second germanium concentration is in a range from 1020 atoms/cm3 to 1035 atoms/cm3.

### Claim 4 (depends on 1)

The method of claim 1, wherein the isolation layer has a thickness that is in a range from 6 nm to 20 nm.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming a conductive via that is disposed between and in physical contact with the backside power rail and the first source/drain region.

### Claim 6 (depends on 5)

The method of claim 5, wherein a width of the conductive via is greater than a width of the first source/drain region.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming a first interconnect structure electrically connected to the backside power rail; and
forming a first plurality of conductive features over the first interconnect structure, wherein the first plurality of conductive features are electrically coupled to the backside power rail.

### Claim 8

A semiconductor device comprising:
a power rail;
an isolation layer over the power rail;
a first channel region over the isolation layer;
a second channel region over the first channel region;
a gate stack disposed between the first channel region and the second channel region, and over the second channel region; and
a first source/drain region adjacent the first channel region and the second channel region, the first source/drain region extending between a first portion of the isolation layer and a second portion of the isolation layer, wherein the first portion of the isolation layer has a trapezoid shape.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising a contact via disposed between and in physical contact with the first source/drain region and the power rail.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the contact via is in physical contact with the first portion of the isolation layer and the second portion of the isolation layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising:
a first interconnect structure electrically connected to the power rail; and
a first plurality of conductive features coupled to the first interconnect structure, wherein the first plurality of conductive features are electrically connected to the first source/drain region through the power rail and the contact via.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, further comprising a dielectric layer disposed between the first portion of the isolation layer and the power rail, and between the second portion of the isolation layer and the power rail, wherein the contact via extends through the dielectric layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a material of the dielectric layer and a material of the isolation layer are different.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the isolation layer comprises aluminum oxide or zirconium oxide.

### Claim 15

A semiconductor device comprising:
a first channel region over a first dielectric layer;
a second channel region over the first channel region;
a gate stack disposed between the first channel region and the second channel region, and over the second channel region;
a first source/drain region and a second source/drain region on opposite sides of the first dielectric layer, the first channel region, the second channel region, and the gate stack; and
a backside power rail on an opposite side of the first dielectric layer as the first channel region, wherein the backside power rail is electrically coupled to the first source/drain region, wherein a thickness of the first dielectric layer is greater than a thickness of the first channel region.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising a conductive via that electrically couples the backside power rail to the first source/drain region.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein a bottom surface of the first source/drain region is level with a bottom surface of the first dielectric layer.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the conductive via is in physical contact with the bottom surface of the first dielectric layer.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the first dielectric layer comprises silicon oxide, silicon nitride, silicon carbon nitride, silicon carbon oxynitride, a metal oxide, or a combination thereof.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein sidewalls of the first dielectric layer are convex or concave.