# US 12,183,675 B2 · Fan-out packages with warpage resistance

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- Number: US 12,183,675 B2
- Document ID: US12183675B2
- Status: Granted
- Kind: B2
- Application number: 16/351,728
- Filed: 2019-03-13
- Published: 2020-09-17
- Granted: 2024-12-31
- Earliest claimed: 2019-03-13
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Rahul Agarwal; Chia-Hao Cheng; Milind S. Bhagavat
- Web page: https://patentgrep.com/patent/US12183675B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/652: Cross-sectional shapes
- H10W 70/655: Fan-out layouts
- H10W 70/685: comprising multiple insulating layers
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip.

## Claims

### Claim 1

A semiconductor chip device, comprising:
a single semiconductor chip;
a first molding layer having internal conductor structures;
a first redistribution layer (RDL) structure positioned on the first molding layer and including fan-out connections to the internal conductor structures;
a second RDL structure positioned on the first RDL structure and including fan-out connections to the first RDL structure, the single semiconductor chip positioned on and electrically connected to the second RDL structure, wherein the first RDL structure is connected to the internal conductor structures of the first molding layer and to the second RDL structure; and
a second molding layer positioned on the second RDL structure and at least partially encapsulating the semiconductor chip.

### Claim 2 (depends on 1)

The semiconductor chip device of claim 1, wherein the internal conductor structures comprise conductive pillars.

### Claim 3 (depends on 1)

The semiconductor chip device of claim 1, wherein the first RDL structure comprises a first amount of redistribution layers and the second RDL structure comprises a second amount of redistribution layers.

### Claim 4 (depends on 1)

The semiconductor chip device of claim 1, wherein the internal conductor structures are electrically connected to plural interconnects, the plural interconnects being configured to electrically connect the semiconductor chip to a circuit board.

### Claim 5 (depends on 1)

The semiconductor chip device of claim 1, wherein the first and second RDL structures comprise plural conductive traces and plural conductive vias.

### Claim 6

A method of manufacturing a semiconductor chip device, comprising:
forming a first molding layer having internal conductor structures;
forming a first redistribution layer (RDL) structure on the first molding layer and including fan-out connections to the internal conductor structures;
forming, after forming the first RDL structure on the first molding layer, a second RDL structure on the first RDL structure and including fan-out connections to the first RDL structure, wherein the first RDL structure is connected to the internal conductor structures of the first molding layer and to the second RDL structure;
mounting a semiconductor chip on and in electrical connection with the second RDL structure; and
forming a second molding layer on the second RDL structure and at least partially encapsulating the semiconductor chip.

### Claim 7 (depends on 6)

The method of claim 6, comprising electrically connecting plural interconnects to the internal conductor structures, the plural interconnects being configured to electrically connect the semiconductor chip to a circuit board.

### Claim 8 (depends on 6)

The method of claim 6, wherein the internal conductor structures comprise conductive pillars.

### Claim 9 (depends on 6)

The method of claim 6, wherein the first RDL structure comprises a first amount of redistribution layers and the second RDL structure comprises a second amount of redistribution layers.

### Claim 10 (depends on 6)

The method of claim 6, wherein forming the internal conductor structures includes performing a plating process.

### Claim 11 (depends on 6)

The method of claim 6, further comprising thinning the second molding layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein thinning the second molding layer includes exposing a surface of the semiconductor chip.

### Claim 13 (depends on 6)

The method of claim 6, wherein the first and second RDL structures comprise plural conductive traces and plural conductive vias.

### Claim 14

A computer system, comprising:
a system board;
wherein the system board comprises one or more chip packages, wherein at least one of the one or more chip packages comprises:
a single semiconductor chip;
a first molding layer having internal conductor structures;
a first redistribution layer (RDL) structure positioned on the first molding layer and including fan-out connections to the internal conductor structures;
a second RDL structure positioned on the first RDL structure and including fan-out connections to the first RDL structure, the single semiconductor chip positioned on and electrically connected to the second RDL structure, wherein the first RDL structure is connected to the internal conductor structures of the first molding layer and to the second RDL structure; and
a second molding layer positioned on the second RDL structure and at least partially encapsulating the semiconductor chip.

### Claim 15 (depends on 14)

The computer system of claim 14, wherein the system board comprises plural interconnects, the plural interconnects being configured to electrically connect the semiconductor chip to the system board.

### Claim 16 (depends on 14)

The computer system of claim 14, wherein the internal conductor structures comprise conductive pillars.

### Claim 17 (depends on 14)

The computer system of claim 14, wherein the first RDL structure comprises a first amount of redistribution layers and the second RDL structure comprises a second amount of redistribution layers.

### Claim 18 (depends on 14)

The computer system of claim 14, wherein the first and second RDL structures comprise plural conductive traces and plural conductive vias.