# US 12,183,670 B2 · Semiconductor device including capacitor and resistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,670 B2 - Document ID: US12183670B2 - Status: Granted - Kind: B2 - Application number: 17/872,892 - Filed: 2022-07-25 - Published: 2022-11-10 - Granted: 2024-12-31 - Earliest claimed: 2020-06-15 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chi-Han Yang - Web page: https://patentgrep.com/patent/US12183670B2 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10D 1/47: Resistors having no potential barriers - H10D 1/68: Capacitors having no potential barriers - H10D 1/692: {Electrodes} - H10D 84/01: Manufacture or treatment - H10D 86/85: characterised by only passive components - H10W 20/063: {by forming conductive members before forming protective insulating material} - H10W 20/496: {Capacitor integral with wiring layers} - H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a capacitor and a resistor. The capacitor includes a first plate, a capacitor dielectric layer disposed over the first plate, and a second plate disposed over the capacitor dielectric layer. The resistor includes a thin film. The thin film of the resistor and the first plate of the capacitor, formed of a same conductive material, are defined in a single patterning process. ## Claims ### Claim 1 A method for forming a semiconductor device, comprising: forming a first Si-rich dielectric layer over a plurality of interconnect structures; depositing a conductive material over the first Si-rich dielectric layer; depositing a dielectric material over the conductive material; etching the conductive material and the dielectric material to concurrently define a thin film of a resistor, a bottom plate of a capacitor, a resistor dielectric layer of the resistor over the thin film, and a capacitor dielectric layer of the capacitor over the bottom plate; forming a top plate of the capacitor over the capacitor dielectric layer, wherein the thin film and the bottom plate of the capacitor each has a first thickness, the resistor dielectric layer and the capacitor dielectric layer each has a second thickness, and a ratio of the first thickness to the second thickness is equal to or less than about 0.25; and forming a second Si-rich dielectric material over the capacitor and the resistor, wherein the second Si-rich dielectric material has a plurality of silicon nanocrystals, and wherein the capacitor and the resistor are partially wrapped by the first Si-rich dielectric material and the second Si-rich dielectric material. ### Claim 2 (depends on 1) The method of claim 1, further comprising: forming, prior to depositing the conductive material, a first vertical interconnect structure, a third vertical interconnect structure, and a fourth vertical interconnect structure, each of which at least partially extends through the first Si-rich dielectric layer. ### Claim 3 (depends on 2) The method of claim 2, wherein the first vertical interconnect structure is configured to electrically connect the bottom plate of the capacitor to a first one of the plurality of interconnect structures. ### Claim 4 (depends on 2) The method of claim 2, wherein the third vertical interconnect structure is configured to electrically connect a first end of the thin film of the resistor to a second one of the plurality of interconnect structures. ### Claim 5 (depends on 2) The method of claim 2, the fourth vertical interconnect structure is configured to electrically connect a second end of the thin film of the resistor to a third one of the plurality of interconnect structures. ### Claim 6 (depends on 1) The method of claim 1, further comprising: forming, subsequently to forming the top plate of the capacitor, a second dielectric layer over the capacitor and the resistor; and forming a second vertical interconnect structure that extends at least partially through the second dielectric layer. ### Claim 7 (depends on 6) The method of claim 6, wherein the second vertical interconnect structure is configured to electrically connect the top plate of the capacitor to a third interconnect structure embedded in a third dielectric layer disposed over the second dielectric layer. ### Claim 8 (depends on 1) The method of claim 1, wherein the dielectric material includes an anti-reflective coating (ARC) material. ### Claim 9 (depends on 1) The method of claim 1, wherein the conductive material includes at least one material selected from the group consisting of Ta, TaN, Ti, TiN, W, WN, NiCr, and SiCr. ### Claim 10 (depends on 1) The method of claim 1, wherein the bottom plate and the capacitor dielectric layer have a first width, and the top plate has a second width, the first width being greater than the second width. ### Claim 11 A method for forming a semiconductor device, comprising: forming a first Si-rich dielectric material over a plurality of first interconnect structures, wherein the first Si-rich dielectric material has a plurality of silicon nanocrystals; depositing a conductive material over the first Si-rich dielectric material; depositing a dielectric material over the conductive material; etching the conductive material and the dielectric material to concurrently define a thin film of a resistor formed by a first segment of the conductive material, a bottom plate of a capacitor formed by a second segment of the conductive material, a resistor dielectric layer of the resistor formed by a first segment of the dielectric material, and a capacitor dielectric layer of the capacitor formed by a second segment of the dielectric material; forming a top plate of the capacitor over the capacitor dielectric layer, wherein the thin film and the bottom plate of the capacitor each has a first thickness, the resistor dielectric layer and the capacitor dielectric layer each has a second thickness, and the first thickness is smaller than the second thickness; and forming a second Si-rich dielectric material over the capacitor and the resistor, wherein the second Si-rich dielectric material has a plurality of silicon nanocrystals, and wherein the capacitor and the resistor are partially wrapped by the first Si-rich dielectric material and the second Si-rich dielectric material. ### Claim 12 (depends on 11) The method of claim 11, further comprising, concurrently with forming the top plate, forming a second interconnect structure over one of the plurality of first interconnect structures and having a bottom surface coplanar with respective bottom surfaces of the bottom plate and the thin film. ### Claim 13 (depends on 11) The method of claim 11, prior to depositing the conductive material, further comprising forming a first vertical interconnect structure, a third vertical interconnect structure, and a fourth vertical interconnect structure, each of which at least partially extends through the first Si-rich dielectric material. ### Claim 14 (depends on 13) The method of claim 13, wherein the first vertical interconnect structure is configured to electrically connect the bottom plate of the capacitor to a first one of the plurality of interconnect structures, the third vertical interconnect structure is configured to electrically connect a first end of the thin film of the resistor to a second one of the plurality of interconnect structures, and the fourth vertical interconnect structure is configured to electrically connect a second end of the thin film of the resistor to a third one of the plurality of interconnect structures, and wherein a ratio of the first thickness to the second thickness is equal to or less than about 0.25. ### Claim 15 (depends on 13) The method of claim 13, further comprising forming a second vertical interconnect structure at least partially extends through a second Si-rich dielectric material deposited over the capacitor and resistor. ### Claim 16 (depends on 15) The method of claim 15, wherein the first vertical interconnect structure and the second vertical interconnect structure are laterally offset from each other. ### Claim 17 (depends on 11) The method of claim 11, wherein the dielectric material includes an anti-reflective coating (ARC) material. ### Claim 18 A method for forming a semiconductor device, comprising: forming a first Si-rich dielectric layer over a first interconnect structure, a second interconnect structure, and a third interconnect structure; depositing a conductive material over the first Si-rich dielectric layer; depositing a dielectric material over the conductive material; performing a single patterning process to concurrently etch the conductive material and the dielectric material to define a thin film of a resistor formed by a first segment of the conductive material, a bottom plate of a capacitor formed by a second segment of the conductive material, a resistor dielectric layer of the resistor formed by a first segment of the dielectric material, and a capacitor dielectric layer of the capacitor formed by a second segment of the dielectric material; forming a top plate of the capacitor over the capacitor dielectric layer; forming a second Si-rich dielectric material over the capacitor and the resistor, wherein the second Si-rich dielectric material has a plurality of silicon nanocrystals, and wherein the capacitor and the resistor are partially wrapped by the first Si-rich dielectric material and the second Si-rich dielectric material; and forming a fourth interconnect structure over the top plate of the capacitor, wherein the thin film and the bottom plate of the capacitor each has a first thickness, the resistor dielectric layer and the capacitor dielectric layer each has a second thickness, and the first thickness is different from the second thickness. ### Claim 19 (depends on 18) The method of claim 18, further comprising: forming a first vertical interconnect structure, a second vertical interconnect structure, and a third vertical interconnect structure below the conductive material, wherein the first vertical interconnect structure electrically connects the first interconnect structure to the bottom plate of the capacitor, the second vertical interconnect structure electrically connects the second interconnect structure to a first end of the thin film of the resistor, and the third vertical interconnect structure electrically connects the third interconnect structure to a second end of the thin film of the resistor; and forming a fourth vertical interconnect structure above the top plate of the capacitor, wherein the fourth vertical interconnect structure electrically connects the top plate of the capacitor to the fourth interconnect structure, wherein a ratio of the first thickness to the second thickness is equal to or less than about 0.25. ### Claim 20 (depends on 18) The method of claim 18, wherein the dielectric material includes an anti-reflective coating (ARC) material.