# US 12,183,668 B2 · Thin-film transistors and MIM capacitors in exclusion zones

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,183,668 B2
- Document ID: US12183668B2
- Status: Granted
- Kind: B2
- Application number: 17/213,144
- Filed: 2021-03-25
- Published: 2022-09-29
- Granted: 2024-12-31
- Earliest claimed: 2021-03-25
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Abhishek A. Sharma; Willy Rachmady; Cheng-Ying Huang; Gilbert Dewey; Rajat Paul
- Web page: https://patentgrep.com/patent/US12183668B2

## CPC

- H10W 20/496: {Capacitor integral with wiring layers}
- H10B 12/05: {Making the transistor}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/716: {having vertical extensions}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/85: characterised by only passive components
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Thin-film transistors and MIM capacitors in exclusion zones are described. In an example, an integrated circuit structure includes a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors. A back-end-of-line (BEOL) structure is above the semiconductor substrate. A thin-film transistor (TFT) and/or a metal-insulator-metal (MIM) capacitor is in the BEOL structure. The TFT and/or MIM capacitor is vertically over the zone that excludes MOS transistors.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors;
a back-end-of-line (BEOL) structure above the semiconductor substrate; and
a first thin-film transistor (TFT) and a second TFT in the BEOL structure, the first TFT vertically over the zone that excludes MOS transistors, and the second TFT vertically over the zone with MOS transistors.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the zone that excludes MOS transistors is a keep out zone (KOZ).

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a through-silicon via (TSV) structure extending through the BEOL structure and the semiconductor substrate, the TSV structure in the zone that excludes MOS transistors.

### Claim 4 (depends on 3)

The integrated circuit structure of claim 3, wherein the first TFT is laterally spaced apart from the TSV structure by a distance of 10 microns or less.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a metal-insulator-metal (MIM) capacitor in the BEOL structure, the MIM capacitor coupled to the first TFT.

### Claim 6

An integrated circuit structure, comprising:
a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors;
a back-end-of-line (BEOL) structure above the semiconductor substrate; and
a first metal-insulator-metal (MIM) capacitor and a second MIM capacitor in the BEOL structure, the first MIM capacitor vertically over the zone that excludes MOS transistors, and the second MIM capacitor vertically over the zone with MOS transistors.

### Claim 7 (depends on 6)

The integrated circuit structure of claim 6, wherein the zone that excludes MOS transistors is a keep out zone (KOZ).

### Claim 8 (depends on 6)

The integrated circuit structure of claim 6, further comprising:
a through-silicon via (TSV) structure extending through the BEOL structure and the semiconductor substrate, the TSV structure in the zone that excludes MOS transistors.

### Claim 9 (depends on 8)

The integrated circuit structure of claim 8, wherein the first MIM capacitor is laterally spaced apart from the TSV structure by a distance of 10 microns or less.

### Claim 10 (depends on 6)

The integrated circuit structure of claim 6, wherein the first MIM capacitor has a cylindrical geometry.

### Claim 11

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors;
a back-end-of-line (BEOL) structure above the semiconductor substrate; and
a first thin-film transistor (TFT) and a second TFT in the BEOL structure, the first TFT vertically over the zone that excludes MOS transistors, and the second TFT vertically over the zone with MOS transistors.

### Claim 12 (depends on 11)

The computing device of claim 11, further comprising:
a memory coupled to the board.

### Claim 13 (depends on 11)

The computing device of claim 11, further comprising:
a communication chip coupled to the board.

### Claim 14 (depends on 11)

The computing device of claim 11, further comprising:
a camera coupled to the board.

### Claim 15 (depends on 11)

The computing device of claim 11, wherein the component is a packaged integrated circuit die.

### Claim 16

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors;
a back-end-of-line (BEOL) structure above the semiconductor substrate; and
a first metal-insulator-metal (MIM) capacitor and a second MIM capacitor in the BEOL structure, the first MIM capacitor vertically over the zone that excludes MOS transistors, and the second MIM capacitor vertically over the zone with MOS transistors.

### Claim 17 (depends on 16)

The computing device of claim 16, further comprising:
a memory coupled to the board.

### Claim 18 (depends on 16)

The computing device of claim 16, further comprising:
a communication chip coupled to the board.

### Claim 19 (depends on 16)

The computing device of claim 16, further comprising:
a camera coupled to the board.

### Claim 20 (depends on 16)

The computing device of claim 16, wherein the component is a packaged integrated circuit die.

### Claim 21

An integrated circuit structure, comprising:
a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors;
a back-end-of-line (BEOL) structure above the semiconductor substrate;
a thin-film transistor (TFT) in the BEOL structure, the TFT vertically over the zone that excludes MOS transistors; and
a through-silicon via (TSV) structure extending through the BEOL structure and the semiconductor substrate, the TSV structure in the zone that excludes MOS transistors.

### Claim 22 (depends on 21)

The integrated circuit structure of claim 21, wherein the TFT is laterally spaced apart from the TSV structure by a distance of 10 microns or less.

### Claim 23

An integrated circuit structure, comprising:
a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors;
a back-end-of-line (BEOL) structure above the semiconductor substrate;
a metal-insulator-metal (MIM) capacitor in the BEOL structure, the first MIM capacitor vertically over the zone that excludes MOS transistors; and
a through-silicon via (TSV) structure extending through the BEOL structure and the semiconductor substrate, the TSV structure in the zone that excludes MOS transistors.

### Claim 24 (depends on 23)

The integrated circuit structure of claim 23, wherein the MIM capacitor is laterally spaced apart from the TSV structure by a distance of 10 microns or less.