# US 12,183,667 B2 · Semiconductor package with power electronics carrier having trench spacing adapted for delamination > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,667 B2 - Document ID: US12183667B2 - Status: Granted - Kind: B2 - Application number: 17/579,727 - Filed: 2022-01-20 - Published: 2023-08-03 - Granted: 2024-12-31 - Earliest claimed: 2022-01-20 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Peter Scherl; Adrian Lis; Christian Neugirg - Web page: https://patentgrep.com/patent/US12183667B2 ## CPC - H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/685: comprising multiple insulating layers - H10W 74/016: {using moulds} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a first power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the first power electronics carrier, and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package, a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance. ## Claims ### Claim 1 A semiconductor package, comprising: a first power electronics carrier comprising a structured metallization layer disposed on an electrically insulating substrate; a power semiconductor die mounted on the first power electronics carrier; and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package; a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package; and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the structured metallization layer of the first power electronics carrier comprises trenches that define a plurality of isolated pads, and wherein the plurality of isolated pads from the first power electronics carrier comprises the first pair of the metal pads. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein the plurality of isolated pads from the first power electronics carrier comprises the second pair of the metal pads, and wherein the second minimum separation distance is greater than a minimum trench separation distance of the trenches in the structured metallization layer of the first power electronics carrier. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the first minimum separation distance is equal to the minimum trench separation distance of the trenches in the structured metallization layer of the first power electronics carrier. ### Claim 5 (depends on 2) The semiconductor package of claim 2, further comprising a second power electronics carrier comprising a structured metallization layer disposed on an electrically insulating substrate, wherein the first and second power electronics carriers are arranged with the power semiconductor die in between the first and second power electronics carriers and with the structured metallization layers of the first and second power electronics carriers facing one another. ### Claim 6 (depends on 5) The semiconductor package of claim 5, wherein the structured metallization layer of the second power electronics carrier comprises trenches that define a plurality of isolated pads, wherein the plurality of isolated pads from the second power electronics carrier comprises the second pair of the metal pads, and wherein the second minimum separation distance is greater than a minimum trench separation distance of the trenches in the structured metallization layer of the second power electronics carrier. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the second separation distance is between two times and twenty times greater than the first minimum separation distance. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the first minimum separation distance is between 0.5 mm and 1.0 mm, and wherein the second separation distance is between 1.0 mm and 20 mm. ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein the first power electronics carrier is any one of: a direct bonded copper substrate, an active metal brazed substrate, or an insulated metal substrate. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the semiconductor package is a power module comprising one or more discrete power devices, wherein the low-voltage difference nodes of the semiconductor package are nodes that are biased below a load voltage of the one or more discrete power devices during all operational states of the power module, and wherein the high-voltage difference nodes of the semiconductor package are nodes that are biased at the load voltage of the one or more discrete power devices during an operational state of the power module. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein the low-voltage difference nodes of the semiconductor package comprise any one or more of: a gate node, a sensing node, and a reference potential node, and wherein the high-voltage difference nodes of the semiconductor package comprise any one or more of: a positive fixed potential node, a negative fixed potential node, a reference potential node, and an output node. ### Claim 12 (depends on 1) The semiconductor package of claim 1, wherein the low-voltage difference nodes of the semiconductor package are nodes that are biased at no greater than 100 V during all operational states of the power module. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein the low-voltage difference nodes of the semiconductor package are nodes that are biased at no greater than 60 V during all operational states of the power module. ### Claim 14 A semiconductor package, comprising: a first power electronics carrier comprising a structured metallization layer disposed on an electrically insulating substrate; a second power electronics carrier comprising a structured metallization layer disposed on an electrically insulating substrate; a first pair of metal pads from the structured metallization layer of the first power electronics carrier that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package; a second pair of metal pads from the structured metallization layer of the second power electronics carrier that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package; a power semiconductor die mounted on the first power electronics carrier; and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the structured metallization layers of the first and second power electronics carriers, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance. ### Claim 15 (depends on 14) The semiconductor package of claim 14, wherein the structured metallization layers of the first and second power electronics carriers each comprise trenches that define a plurality of isolated pads, wherein the first minimum separation distance is equal to a minimum trench separation distance of the structured metallization layer of the first power electronics carrier, and wherein the second minimum separation distance is equal to a minimum trench separation distance of the trenches in the structured metallization layer of the second power electronics carrier. ### Claim 16 A method of producing a semiconductor package, the method comprising: providing a first power electronics carrier comprising a structured metallization layer disposed on an electrically insulating substrate; mounting a power semiconductor die on the first power electronics carrier; forming an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the structured metallization layer of the first power electronics carrier, wherein the semiconductor package comprises a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package and a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance. ### Claim 17 (depends on 16) The method of claim 16, wherein the structured metallization layer of the first power electronics carrier comprises trenches that define a plurality of isolated pads, and wherein the plurality of isolated pads from the first power electronics carrier comprises the first pair of the metal pads. ### Claim 18 (depends on 16) The method of claim 16, wherein forming the encapsulant body comprises a molding process. ### Claim 19 (depends on 18) The method of claim 18, wherein the plurality of isolated pads from the first power electronics carrier comprises the second pair of the metal pads, and wherein the structured metallization layer of the first power electronics carrier is encapsulated by the encapsulant body without performing an adhesion promotor step on the structured metallization layer of the first power electronics carrier. ### Claim 20 (depends on 18) The method of claim 18, further comprising: providing a second power electronics carrier comprising a structured metallization layer disposed on an electrically insulating substrate; and arranging the power semiconductor die in between the first and second power electronics carriers and with the structured metallization layers of the first and second power electronics carriers facing one another, wherein forming the encapsulant body encapsulates the structured metallization layer of the second power electronics carrier, and wherein the structured metallization layer of the second power electronics carrier is encapsulated by the encapsulant body without performing an adhesion promotor step on the structured metallization layer of the second power electronics carrier.