# US 12,183,666 B2 · Ceramic laminated substrate, module, and method of manufacturing ceramic laminated substrate

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- Number: US 12,183,666 B2
- Document ID: US12183666B2
- Status: Granted
- Kind: B2
- Application number: 18/149,205
- Filed: 2023-01-03
- Published: 2023-05-11
- Granted: 2024-12-31
- Earliest claimed: 2018-07-27
- Assignees: Murata Manufacturing Co., Ltd.
- Applicants: Murata Manufacturing Co., Ltd.
- Inventors: Takuya Goitsuka
- Web page: https://patentgrep.com/patent/US12183666B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H05K 1/113: {Via provided in pad; Pad over filled via}
- H05K 1/18: structurally associated with non-printed electric components (H05K1/16 takes precedence)
- H05K 3/34: by soldering
- H05K 3/46: Manufacturing multilayer circuits
- H05K 3/4629: {laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets}
- H10W 70/68: Shapes or dispositions thereof
- H10W 90/00: Package configurations
- H05K 3/244: {Finish plating of conductors, especially of copper conductors, e.g. for pads or lands (selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3465)}
- H05K 2201/094: Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
- H10W 70/685: comprising multiple insulating layers
- H10W 70/692: Ceramics or glasses
- H10W 72/072: {of bump connectors}
- H10W 72/07254: {changes in dispositions}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

Provided is a ceramic laminated substrate which is formed on an electronic component to be mounted and is less likely to cause mounting defects even if there is irregularity in the height of solders. The ceramic laminated substrate includes: a ceramic laminate on which ceramic layers are laminated; via conductors; terminal electrodes; and a land electrode. The land electrode has a first land electrode and a second land electrode that are used to join different terminal electrodes of a single electronic component. The area of the first land electrode is smaller than the area of the second land electrode, and the first land electrode has a bump electrode and a plating layer, the second land electrode has a membrane electrode and plating layers, and the height of the first land electrode is formed higher than the height of the second land electrode.

## Claims

### Claim 1

A ceramic laminated substrate comprising:
a ceramic laminate having a first main surface and a second main surface, and including a plurality of laminated ceramic layers;
via conductors provided inside the laminate;
a terminal electrode provided on the first main surface; and
a land electrode for mounting an electronic component, the land electrode being provided on the second main surface,
wherein:
the land electrode has at least one first land electrode and at least one second land electrode, the second land electrode having a larger area than the first land electrode;
the first land electrode has a bump electrode provided on a surface of one of the via conductors exposed from the second main surface of the laminate, and a first plating layer provided on a surface of the bump electrode and covering an entire surface of the bump electrode;
the second land electrode has a second plating layer provided on a surface of another one of the via conductors exposed from the second main surface of the laminate; and
in the second main surface of the laminate, one of the via conductors provided under the first land electrode has an exposed area smaller than an exposed area of one of the via conductors provided under the second land electrode, and a height of the first land electrode is higher than a height of the second land electrode.

### Claim 2 (depends on 1)

The ceramic laminated substrate according to claim 1, wherein a main component of the one of the via conductors provided under the first land electrode is identical with a main component of the bump electrode of the first land electrode.

### Claim 3 (depends on 1)

The ceramic laminated substrate according to claim 1, wherein, on the second main surface of the laminate, the first land electrode has a circular planar shape and the second land electrode has an oval planar shape.

### Claim 4 (depends on 1)

A module comprising:
the ceramic laminated substrate according to claim 1; and
an electronic component mounted on the ceramic laminated substrate,
wherein:
the electronic component is a semiconductor device including a plurality of terminal electrodes; and
at least one of the terminal electrodes of the semiconductor device is bonded to the first land electrode, and at least one of other ones of the terminal electrodes of the semiconductor device is bonded to the second land electrode.