# US 12,183,665 B2 · Semiconductor package

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,183,665 B2
- Document ID: US12183665B2
- Status: Granted
- Kind: B2
- Application number: 18/423,229
- Filed: 2024-01-25
- Published: 2024-05-16
- Granted: 2024-12-31
- Earliest claimed: 2021-05-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Myungsam Kang; Youngchan Ko; Jeongseok Kim; Kyung Don Mun
- Web page: https://patentgrep.com/patent/US12183665B2

## CPC

- H10W 70/685: comprising multiple insulating layers
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 74/014: {using batch processing}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/611: {for connecting multiple chips together}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/20: Configurations of stacked chips
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.

## Claims

### Claim 1

A method of manufacturing a semiconductor package, comprising:
providing a carrier substrate having a connection hole on a first carrier substrate;
providing first and second semiconductor chips in the connection hole on the first carrier substrate;
forming a molding layer covering the carrier substrate and upper surfaces of the first and second semiconductor chips;
attaching a second carrier substrate on the molding layer;
removing the first carrier substrate;
turning the second carrier substrate to allow lower surfaces of the first and second semiconductor chips to face upwards;
forming a first redistribution substrate on the lower surfaces of the first and second semiconductor chips;
mounting a connection semiconductor chip and a capacitor chip on the first redistribution substrate, the capacitor chip horizontally spaced apart from the connection semiconductor chip;
forming an interposer molding layer covering upper surfaces of the connection semiconductor chip; and
forming a second redistribution substrate on the interposer molding layer.

### Claim 2 (depends on 1)

The method of manufacturing the semiconductor package of claim 1, further comprising forming conductive posts on the first redistribution substrate before forming the interposer molding layer,
wherein the conductive posts connect the first redistribution substrate and the second redistribution substrate.

### Claim 3 (depends on 2)

The method of manufacturing the semiconductor package of claim 2, further comprising grinding the interposer molding layer to expose surfaces of the conductive posts before forming the second redistribution substrate.

### Claim 4 (depends on 3)

The method of manufacturing the semiconductor package of claim 3, wherein an upper surface of the connection semiconductor chip is not exposed during grinding the interposer molding layer.

### Claim 5 (depends on 1)

The method of manufacturing the semiconductor package of claim 1, after forming the second redistribution substrate, further comprising:
turning the second carrier substrate upside down again to locate the lower surfaces of the first and second semiconductor chips facing downward;
removing the second carrier substrate; and
grinding the molding layer to expose upper surfaces of the first and second semiconductor chips.

### Claim 6 (depends on 5)

The method of manufacturing the semiconductor package of claim 5, wherein the molding layer covers an upper surface and a sidewall of the carrier substrate, and sidewalls of the first and second semiconductor chips.

### Claim 7 (depends on 5)

The method of manufacturing the semiconductor package of claim 5, further comprising disposing a thermal dissipation plate contacting at least one of the upper surfaces of the first and semiconductor chips after grinding the molding layer.

### Claim 8 (depends on 1)

The method of manufacturing the semiconductor package of claim 1, wherein an upper surface of the first semiconductor chip is at a lever higher than a level of an upper surface of the carrier substrate.

### Claim 9 (depends on 1)

The method of manufacturing the semiconductor package of claim 1, wherein mounting the capacitor chip horizontally spaced apart from the connection semiconductor chip on the first redistribution before forming the interposer molding layer.

### Claim 10 (depends on 1)

The method of manufacturing the semiconductor package of claim 1, wherein the first redistribution substrate includes a first redistribution dielectric layer and first redistribution patterns in the first redistribution dielectric layer, and
wherein each of the first redistribution patterns includes a first wire part and a first via part on the first wire part.

### Claim 11 (depends on 10)

The method of manufacturing the semiconductor package of claim 10, wherein the second redistribution substrate includes a second redistribution dielectric layer and second redistribution patterns in the second redistribution dielectric layer,
wherein each of the second redistribution patterns includes a second wire part and a second via part on the second wire part.

### Claim 12 (depends on 1)

The method of manufacturing the semiconductor package of claim 1, wherein an upper surface and a lower surface of the connection semiconductor chip are covered by the interposer molding layer.

### Claim 13 (depends on 1)

The method of manufacturing the semiconductor package of claim 1, wherein
a first portion of the connection semiconductor chip vertically overlaps a portion of the first semiconductor chip, and
a second portion of the connection semiconductor chip vertically overlaps a portion of the second semiconductor chip.

### Claim 14

A method of manufacturing a semiconductor package, comprising:
providing a carrier substrate having a connection hole on a first carrier substrate;
providing first and second semiconductor chips in the connection hole on the first carrier substrate;
forming a preliminary molding layer covering the carrier substrate and upper surfaces of the first and second semiconductor chips;
attaching a second carrier substrate on the preliminary molding layer;
removing the first carrier substrate;
turning the second carrier substrate to allow lower surfaces of the first and second semiconductor chips to face upwards;
forming a first redistribution substrate including a first redistribution dielectric layer and first redistribution patterns in the first redistribution dielectric layer, on the lower surfaces of the first and second semiconductor chips;
forming conductive patterns connected to the first redistribution patterns on the first redistribution substrate;
forming conductive posts on the conductive patterns on an edge region of the first redistribution substrate;
mounting a connection semiconductor chip connected to the conductive patterns and a capacitor chip horizontally spaced apart from the connection semiconductor chip on a center region of the first redistribution substrate;
forming an interposer molding layer covering upper surfaces of the connection semiconductor chip;
forming a second redistribution substrate including a second redistribution dielectric layer and second redistribution patterns in the second redistribution dielectric layer, on the interposer molding layer,
turning the second carrier substrate again to allow the lower surfaces of the first and second semiconductor chips to face downwards;
removing the second carrier substrate; and
forming a molding layer by grinding the preliminary molding layer to expose upper surfaces of the first and second semiconductor chips.

### Claim 15 (depends on 14)

The method of manufacturing the semiconductor package of claim 14, further comprising disposing a thermal dissipation plate contacting at least one of the upper surfaces of the first and semiconductor chips after forming a molding layer.

### Claim 16 (depends on 14)

The method of manufacturing the semiconductor package of claim 14, an upper surface and lower surface of the connection semiconductor chip are covered by the interposer molding layer.

### Claim 17 (depends on 14)

The method of manufacturing the semiconductor package of claim 14, the molding layer covers an upper surface of the carrier substrate, and
the molding layer exposes a top surface of the first semiconductor chip and a top surface of the second semiconductor chip.

### Claim 18 (depends on 14)

The method of manufacturing the semiconductor package of claim 14, wherein the carrier substrate includes a conductive structure and a base layer,
wherein the conductive structure is connected to the first redistribution substrate.

### Claim 19 (depends on 18)

The method of manufacturing the semiconductor package of claim 18, wherein the conductive structure is connected to the conductive posts on the edge region of the first redistribution substrate.

### Claim 20 (depends on 14)

The method of manufacturing the semiconductor package of claim 14, wherein
a first portion of the connection semiconductor chip vertically overlaps a portion of the first semiconductor chip, and
a second portion of the connection semiconductor chip vertically overlaps a portion of the second semiconductor chip.