# US 12,183,664 B2 · Semiconductor package

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- Number: US 12,183,664 B2
- Document ID: US12183664B2
- Status: Granted
- Kind: B2
- Application number: 17/381,869
- Filed: 2021-07-21
- Published: 2022-05-19
- Granted: 2024-12-31
- Earliest claimed: 2020-11-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Ju-Il Choi; Gyuho Kang; Seong-Hoon Bae; Jin Ho An; Jeonggi Jin; Atsushi Fujisaki
- Web page: https://patentgrep.com/patent/US12183664B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/655: Fan-out layouts
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/20: Configurations of stacked chips
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

## Claims

### Claim 1

A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip mounted on a top surface of the redistribution substrate; and
a conductive terminal provided on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion; and
an insulating layer covering top and side surfaces of the under-bump pattern, and
wherein a central portion of a bottom surface of the via portion is provided at a level higher than an edge portion of the bottom surface of the via portion,
wherein the bottom surface of the via portion is curvedly recessed in a direction toward the wire portion,
wherein the via portion comprises a seed pattern and a conductive pattern on the seed pattern, and
wherein the conductive terminal contacts the seed pattern and the conductive pattern of the via portion.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the central portion of the bottom surface of the via portion is provided at a level higher than the bottom surface of the redistribution substrate.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein a vertical distance from the bottom surface of the redistribution substrate to the central portion of the bottom surface of the via portion is in a range of 500 nm to 1 μm.

### Claim 4 (depends on 2)

The semiconductor package of claim 2, wherein a ratio of a vertical distance, which is a distance from the bottom surface of the redistribution substrate to the central portion of the bottom surface of the via portion, to a width of the via portion is in a range of 0.01 to 0.2.

### Claim 5 (depends on 1)

The semiconductor package of claim 1,
wherein the redistribution substrate further comprises a redistribution pattern provided on the under-bump pattern,
wherein the under-bump pattern comprises a conductive pattern, which is interposed between the conductive terminal and the redistribution pattern, and a seed pattern, which is provided between the conductive pattern and the insulating layer, and
wherein the conductive pattern is in direct contact with the conductive terminal.

### Claim 6 (depends on 5)

The semiconductor package of claim 5, wherein an interface between the conductive terminal and the conductive pattern is convexly curved toward the wire portion of the under-bump pattern.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein a vertical distance from the bottom surface of the redistribution substrate to the top surface of the under-bump pattern is in a range of 15 μm to 25 μm.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the topmost portion of the conductive terminal is located at a level higher than the bottom surface of the redistribution substrate.

### Claim 9 (depends on 1)

The semiconductor package of claim 1,
wherein the redistribution substrate further comprises a redistribution pattern provided on the under-bump pattern, and
wherein a ratio of a height of the redistribution pattern to a height of the under-bump pattern is in a range of 0.1 to 0.2.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein a ratio of a width of the via portion to a width of the wire portion of the under-bump pattern is in a range of 0.7 to 0.8.

### Claim 11

A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip mounted on a top surface of the redistribution substrate; and
a conductive terminal provided on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
an under-bump pattern including a first via portion in contact with the conductive terminal and a wire portion on the first via portion;
an insulating layer contacting a side surface of the under-bump pattern; and
redistribution patterns provided on the under-bump pattern,
wherein the uppermost redistribution patterns of the redistribution patterns are connected to the semiconductor chip,
wherein at least one of the uppermost redistribution patterns comprises a second via portion and a pad portion on the second via portion,
wherein the wire portion comprises a seed pattern and a conductive pattern on the seed pattern,
wherein side surfaces of the seed pattern and the conductive pattern of the wire portion are aligned in a vertical direction,
wherein the bottom surface of the first via portion is curvedly recessed in a direction toward the wire portion,
wherein the conductive terminal contacts the seed pattern and the conductive pattern of the first via portion of the under-bump pattern,
wherein an uppermost surface of the conductive terminal is at a higher level than a lowermost surface of the insulating layer, and
wherein only a top surface of the conductive pattern of the pad portion of the at least one of the uppermost redistribution patterns includes a recessed portion.

### Claim 12 (depends on 11)

The semiconductor package of claim 11, wherein a depth of the recessed portion is in a range of 500 nm to 1 μm.

### Claim 13 (depends on 11)

The semiconductor package of claim 11, wherein the largest width of the recessed portion is in a range of 200 nm to 300 nm.

### Claim 14 (depends on 11)

The semiconductor package of claim 11, further comprising:
a chip connection terminal interposed between the semiconductor chip and the at least one of the uppermost redistribution patterns,
wherein the chip connection terminal is extended into the recessed portion.

### Claim 15 (depends on 11)

The semiconductor package of claim 11, further comprising:
an insulating layer covering top and side surfaces of the under-bump pattern,
wherein the under-bump pattern comprises a conductive pattern, which is interposed between the conductive terminal and the redistribution patterns, and a seed pattern, which is provided between the conductive pattern and the insulating layer, and
wherein each of the conductive pattern and the seed pattern of the under-bump pattern is in physical contact with the conductive terminal.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein the seed pattern of the under-bump pattern is provided to expose at least a portion of a bottom surface of the conductive pattern of the under-bump pattern adjacent to the conductive terminal.

### Claim 17

A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip mounted on a top surface of the redistribution substrate;
a chip connection terminal provided between the redistribution substrate and the semiconductor chip;
an under-fill layer surrounding the chip connection terminal;
a mold layer covering side and top surfaces of the semiconductor chip and side surfaces of the under-fill layer; and
a conductive terminal provided on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion;
redistribution patterns provided on the under-bump pattern; and
an insulating layer covering the under-bump pattern and the redistribution patterns,
wherein each of the redistribution patterns comprises a via portion, which is in contact with another one of the redistribution patterns adjacent thereto or the under-bump pattern, and a wire portion, which is provided on the via portion,
wherein a central portion of a bottom surface of the via portion of the under-bump pattern is provided at a level higher than an edge portion of the bottom surface of the via portion of the under-bump pattern,
wherein the bottom surface of the via portion is curvedly recessed in a direction toward the wire portion,
wherein the via portion comprises a seed pattern and a conductive pattern on the seed pattern, and
wherein the conductive terminal contacts the seed pattern and the conductive pattern of the via portion.