# US 12,183,663 B2 · Semiconductor device

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- Number: US 12,183,663 B2
- Document ID: US12183663B2
- Status: Granted
- Kind: B2
- Application number: 18/510,204
- Filed: 2023-11-15
- Published: 2024-03-14
- Granted: 2024-12-31
- Earliest claimed: 2018-04-11
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Kazuki Okuyama; Shuntaro Takahashi; Motoharu Haga; Shingo Yoshida; Kazuhisa Kumagai; Hajime Okuda
- Web page: https://patentgrep.com/patent/US12183663B2

## CPC

- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 76/48: Fillings including materials for absorbing or reacting with moisture or other undesired substances
- H10D 10/421: {having both emitter-base and base-collector junctions ending at the same surface of the body}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 84/403: {Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors}
- H10W 10/051: {of isolation region based on field-effect}
- H10W 10/50: Isolation regions based on field-effect
- H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60)
- H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps}
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 70/421: {Shapes or dispositions}
- H10W 70/427: {Bent parts}
- H10W 70/457: {of metallic layers on leadframes}
- H10W 70/461: {specially adapted for cooling}
- H10W 70/465: {Bumps or wires}
- H10W 72/075: {of bond wires}
- H10W 74/016: {using moulds}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10D 1/66: Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
- H10D 30/665: {having edge termination structures}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5366: {the bond wires having kinks}
- H10W 72/5438: {the bond wires having multiple connections on the same bond pad}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/652: {comprising metals or metalloids, e.g. silver}
- H10W 72/655: {of outermost layers of multilayered strap connectors, e.g. material of a coating}
- H10W 72/871: {Bond wires and strap connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor element comprising:
a substrate having a transistor formation region in which a transistor is formed and which is shaped to be non-quadrangular, and
an electrode pad on the transistor formation region;
a surface protection film that covers the electrode pad; and
a first connection member connected to the electrode pad at one location, wherein
the first connection member is a bonding wire,
the electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad,
in the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region to increase active clamp capacity,
a center position of the connection region coincides with the center of gravity position of the transistor formation region, and
the surface protection film has an opening for the connection region.

### Claim 2

A semiconductor device, comprising:
a semiconductor element comprising:
a substrate having a transistor formation region in which a transistor is formed and which is shaped to be non-quadrangular, and
an electrode pad on the transistor formation region;
a surface protection film that covers the electrode pad; and
a first connection member connected to the electrode pad at multiple locations, wherein
the first connection member is a bonding wire,
the transistor formation region is divided into divided regions having equal areas in accordance with the number of locations where the first connection member is connected,
the electrode pad is arranged to cover a center of gravity of each of the divided regions in a plan view,
in the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of each of the divided regions to increase active clamp capacity,
a center position of the connection region coincides with the center of gravity position of each of the divided regions, and
the surface protection film has an opening for the connection region.

### Claim 3

A semiconductor device, comprising:
a semiconductor element comprising:
a substrate having a transistor formation region in which a transistor is formed and which is shaped to be non-quadrangular, and
an electrode pad on the transistor formation region;
a surface protection film that covers the electrode pad; and
first connection members connected to the electrode pad, wherein
each of the first connection members is a bonding wire,
the transistor formation region is divided into divided regions having equal areas in accordance with the number of the first connection members,
the electrode pad is arranged to cover a center of gravity of each of the divided regions in a plan view,
in the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of each of the divided regions to increase active clamp capacity,
a center position of the connection region coincides with the center of gravity position of each of the divided regions, and
the surface protection film has an opening for the connection region.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, wherein the divided regions are equally divided to approach a square.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor element includes a power transistor and a control electrode pad connected to a control terminal of the power transistor, the semiconductor device comprising:
a first lead frame on which the semiconductor element is mounted;
a second lead frame connected to a second connection member, wherein the second connection member has one end connected to the control electrode pad and another end connected to the second lead frame; and
a third lead frame connected to the first connection member, wherein the first connection member has one end connected to the semiconductor element and another end connected to the third lead frame.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein
the first lead frame and the third lead frame are formed including copper,
the first connection member is formed including aluminum, and
a surface of at least one of the first lead frame and the third lead frame includes a plating layer.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein
the first lead frame includes a first island on which the semiconductor element is mounted, and
a surface of the first island on which the semiconductor element is mounted includes a plating layer.

### Claim 8 (depends on 6)

The semiconductor device according to claim 6, wherein
the third lead frame includes a third island to which the first connection member is connected, and
a surface of the third island where the first connection member is connected includes a plating layer.

### Claim 9 (depends on 5)

The semiconductor device according to claim 5, wherein
the second lead frame is formed including copper and includes a second island to which the second connection member is connected,
the second connection member is formed including aluminum, and
a surface of the third island where the second connection member is connected includes a plating layer.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, wherein
the first connection member is wedge-bonded to the electrode pad and includes a connection portion connected to the electrode pad, and
in a plan view, the connection portion extends from the semiconductor element toward the third island.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a temperature sensor arranged on the substrate outside the electrode pad,
wherein the temperature sensor is located in a region outside the electrode pad where heat is most concentrated when the semiconductor device is driven.

### Claim 12 (depends on 3)

The semiconductor device according to claim 3, wherein the divided regions are equally divided to approach a square.

### Claim 13 (depends on 2)

The semiconductor device according to claim 2, wherein the semiconductor element includes a power transistor and a control electrode pad connected to a control terminal of the power transistor, the semiconductor device further comprising:
a first lead frame on which the semiconductor element is mounted;
a second lead frame connected to a second connection member, wherein the second connection member has one end connected to the control electrode pad and another end connected to the second lead frame; and
a third lead frame connected to the first connection member, wherein the first connection member has one end connected to the semiconductor element and another end connected to the third lead frame.

### Claim 14 (depends on 3)

The semiconductor device according to claim 3, wherein the semiconductor element includes a power transistor and a control electrode pad connected to a control terminal of the power transistor, the semiconductor device further comprising:
a first lead frame on which the semiconductor element is mounted;
a second lead frame connected to a second connection member, wherein the second connection member has one end connected to the control electrode pad and another end connected to the second lead frame; and
a third lead frame connected to the first connection member, wherein the first connection member has one end connected to the semiconductor element and another end connected to the third lead frame.

### Claim 15 (depends on 2)

The semiconductor device according to claim 2, further comprising:
a temperature sensor arranged on the substrate outside the electrode pad,
wherein the temperature sensor is located in a region outside the electrode pad where heat is most concentrated when the semiconductor device is driven.

### Claim 16 (depends on 3)

The semiconductor device according to claim 3, further comprising:
a temperature sensor arranged on the substrate outside the electrode pad,
wherein the temperature sensor is located in a region outside the electrode pad where heat is most concentrated when the semiconductor device is driven.