# US 12,183,662 B2 · Signal isolator having enhanced creepage characteristics > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,662 B2 - Document ID: US12183662B2 - Status: Granted - Kind: B2 - Application number: 18/618,259 - Filed: 2024-03-27 - Published: 2024-07-11 - Granted: 2024-12-31 - Earliest claimed: 2019-09-18 - Assignees: Allegro MicroSystems, LLC - Applicants: Allegro MicroSystems, LLC - Inventors: Robert A. Briano; Shixi Louis Liu; William P. Taylor - Web page: https://patentgrep.com/patent/US12183662B2 ## CPC - H10W 70/411: {Chip-supporting parts, e.g. die pads} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/421: {Shapes or dispositions} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/811: {Multiple chips on leadframes} - H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping} - H10W 72/07236: {Soldering or alloying} - H10W 72/073: {of die-attach connectors} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/075: {of bond wires} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics} - H10W 72/354: {comprising polymers} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5473: {multiple bond wires connected to a common bond pad} - H10W 72/551: {Materials of bond wires} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/127: {characterised by arrangements for sealing or adhesion} - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/753: {between laterally-adjacent chips} - H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, an isolator includes a leadframe having first and second die paddles each having opposed first and second surfaces, a first die supported by the first surface of the first die paddle, and a second die supported by the first surface of the second die paddle. The first and second die paddles are configured enhanced creepage characteristics. ## Claims ### Claim 1 A leadless signal isolator IC package, comprising: a leadframe having first and second die paddles each having opposed first and second surfaces; a first die supported by the first surface of the first die paddle; and a second die supported by the first surface of the second die paddle, wherein the second surface of the first die paddle is exposed on an exterior surface of the package, and wherein the second surface of the second die paddle is exposed on the exterior surface of the package, wherein the first die has a first width and the second die has a second width, wherein a width of the second surface of the first die paddle is less than the first width of the first die along an entire length of the first die and edges of the first die along the length of the first die are outside of edges of the exposed second surface of the first die paddle, and wherein a width of the first surface of the first die paddle is greater than the first width of the die along the entire length of the first die. ### Claim 2 (depends on 1) The signal isolator IC package according to claim 1, wherein a width of the second surface of the second die paddle is less than the second width of the second die along an entire length of the second die and edges of the second die along the length of the second die are outside of edges of the exposed second surface of the second die paddle. ### Claim 3 (depends on 1) The signal isolator IC package according to claim 1, wherein the first die includes pads located within the width of the second surface of the first die paddle. ### Claim 4 (depends on 1) The signal isolator IC package according to claim 1, wherein the first die includes a first voltage domain and the second die includes a second voltage domain. ### Claim 5 (depends on 1) The signal isolator package according to claim 1, wherein the first die paddle comprises a middle portion having a first thickness and outer portions having a second thickness that is less than the first thickness. ### Claim 6 (depends on 1) The signal isolator package according to claim 1, wherein the first die includes pads located within the width of the second surface of the first die paddle, and further including at least one wirebond connected to at least one of the pads. ### Claim 7 A method for providing a leadless signal isolator IC package, comprising: employing a leadframe having first and second die paddles each having opposed first and second surfaces; employing a first die supported by the first surface of the first die paddle; and employing a second die supported by the first surface of the second die paddle, wherein the second surface of the first die paddle is exposed on an exterior surface of the package, and wherein the second surface of the second die paddle is exposed on the exterior surface of the package, wherein the first die has a first width and the second die has a second width, wherein a width of the second surface of the first die paddle is less than the first width of the first die along an entire length of the first die and edges of the first die along the length of the first die are outside of edges of the exposed second surface of the first die paddle, and wherein a width of the first surface of the first die paddle is greater than the first width of the die along the entire length of the first die. ### Claim 8 (depends on 7) The method according to claim 7, wherein a width of the second surface of the second die paddle is less than the second width of the second die along an entire length of the second die and edges of the second die along the length of the second die are outside of edges of the exposed second surface of the second die paddle. ### Claim 9 (depends on 7) The method according to claim 7, wherein the first die includes pads located within the width of the second surface of the first die paddle. ### Claim 10 (depends on 7) The method according to claim 7, wherein the first die includes a first voltage domain and the second die includes a second voltage domain. ### Claim 11 (depends on 7) The method according to claim 7, wherein the first die paddle comprises a middle portion having a first thickness and outer portions having a second thickness that is less than the first thickness. ### Claim 12 (depends on 7) The method according to claim 7, wherein the first die includes pads located within the width of the second surface of the first die paddle, and further including at least one wirebond connected to at least one of the pads.