# US 12,183,660 B2 · Semiconductor device including through-silicon via and method of forming the same

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- Number: US 12,183,660 B2
- Document ID: US12183660B2
- Status: Granted
- Kind: B2
- Application number: 17/736,212
- Filed: 2022-05-04
- Published: 2023-04-13
- Granted: 2024-12-31
- Earliest claimed: 2021-10-13
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jeonil Lee; Jongmin Lee; Jimin Choi; Yeonjin Lee
- Web page: https://patentgrep.com/patent/US12183660B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/0698: {Local interconnections}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate comprising a first surface and a second surface opposing the first surface;
a via insulating layer extending through the substrate;
a through-silicon via extending through the via insulating layer, a center of the through-silicon via misaligned from a center of the via insulating layer;
a blocking layer on the first surface;
a first insulating layer on the blocking layer; and
a contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein,
the through-silicon via comprises a first side surface and a second side surface opposing the first side surface,
the via insulating layer comprises a first portion adjacent to the first side surface, and a second portion adjacent to the second side surface, and
a first horizontal width of the first portion is greater than a second horizontal width of the second portion.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein a distance between a lowermost end of the contact plug and the second surface is less than or equal to a distance between the first surface and the second surface.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein a distance between a lowermost end of the contact plug and the second surface is less than or equal to a distance between an uppermost end of the via insulating layer and the second surface.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the via insulating layer has a width relatively increasing as the via insulating layer extends toward the first surface, and the via insulating layer has a width relatively decreasing as the via insulating layer extends toward the second surface.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the through-silicon via has a width relatively decreasing as the through-silicon via extends toward the first surface, and the through-silicon via has a width relatively increasing as the through-silicon via extends toward the second surface.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein a horizontal width of the through-silicon via is greater than a horizontal width of the contact plug.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the through-silicon via contacts a lower surface and a side surface of the contact plug.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the through-silicon via contacts the blocking layer.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein an uppermost end of the through-silicon via is coplanar with the first surface.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the blocking layer extends on the via insulating layer.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, wherein,
the via insulating layer comprises silicon oxide, and
the blocking layer comprises silicon nitride.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1, wherein:
the contact plug comprises tungsten (W), and
the through-silicon via comprises copper (Cu).

### Claim 14 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a second insulating layer on the first insulating layer; and
a wiring in the second insulating layer and contacting the contact plug,
wherein the wiring comprises copper (Cu).

### Claim 15 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a spacer having a uniform thickness between the through-silicon via and the via insulating layer.

### Claim 16 (depends on 1)

A method of forming the semiconductor device of claim 1, comprising:
forming the via insulating layer extending through the substrate, the forming the via insulating layer comprising performing a first thin film formation process at between 400° C. to 1,300° C.;
forming the contact plug; and
forming the through-silicon via after formation of the via insulating layer and the contact plug.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising:
forming a transistor on the substrate after forming the via insulating layer and before forming the through-silicon via.

### Claim 18 (depends on 16)

The method according to claim 16, further comprising:
forming a spacer between the through-silicon via and the via insulating layer after forming the via insulating layer and the contact plug,
wherein the forming the spacer comprises performing a second thin film formation process at a lower temperature than the forming the via insulating layer.

### Claim 19 (depends on 18)

The method according to claim 18, wherein the forming the spacer comprises the second thin film formation process, which is performed at between 150° C. to 400° C.

### Claim 20

A semiconductor device comprising:
a substrate comprising a first surface and a second surface opposing the first surface;
a via insulating layer extending through the substrate, the via insulating layer having a width relatively increasing as the via insulating layer extends toward the first surface and having a width relatively decreasing as the via insulating layer extends toward the second surface;
a through-silicon via extending through the via insulating layer, the through-silicon via having a width relatively decreasing as the through-silicon via extends toward the first surface and having a width relatively increasing as the through-silicon via extends toward the second surface;
a blocking layer on the first surface;
a first insulating layer on the blocking layer; and
a contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer.