# US 12,183,659 B2 · Embedded cooling assemblies for advanced device packaging and methods of manufacturing the same

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- Number: US 12,183,659 B2
- Document ID: US12183659B2
- Status: Granted
- Kind: B2
- Application number: 18/397,505
- Filed: 2023-12-27
- Published: 2024-07-04
- Granted: 2024-12-31
- Earliest claimed: 2022-12-29
- Assignees: Adeia Semiconductor Bonding Technologies Inc.
- Applicants: Adeia Semiconductor Bonding Technologies Inc.
- Inventors: Belgacem Haba
- Web page: https://patentgrep.com/patent/US12183659B2

## CPC

- H10W 40/47: by flowing liquids, e.g. forced water cooling
- H10W 40/43: by flowing gases, e.g. forced air cooling
- H10W 40/73: for cooling by change of state
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/90: Bond pads, in general
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/011: {Manufacture or treatment of pads or other interconnections to be direct bonded}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/00: Package configurations
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/796: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The package cover generally has an inlet opening and an outlet opening disposed there through. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package may include a material layer between the package cover and the cold plate. The cold plate may include a patterned first side and an opposite second side. The patterned first side may include a base surface and sidewalls extending downward from the base surface, where the base surface is spaced apart from the semiconductor device to collectively define a coolant channel. Here, the coolant channel is in fluid communication with the inlet opening and the outlet opening through openings disposed through respective portions of the material layer.

## Claims

### Claim 1

A device package comprising:
a package substrate;
a package cover disposed on the package substrate, the package cover having an inlet opening and an outlet opening disposed therethrough;
an integrated cooling assembly disposed between the package substrate and the package cover, the integrated cooling assembly comprising a semiconductor device and a cold plate attached to the semiconductor device; and
a material layer disposed between the package cover and the cold plate, wherein:
the cold plate comprises a patterned first side and an opposite second side;
the patterned first side comprises a base surface and sidewalls extending downwardly from the base surface;
the base surface is spaced apart from the semiconductor device to collectively define a coolant channel therebetween; and
the coolant channel is in fluid communication with the inlet opening and the outlet opening through openings disposed through respective portions of the material layer.

### Claim 2 (depends on 1)

The device package of claim 1, the cold plate is attached to the semiconductor device by direct dielectric bonds.

### Claim 3 (depends on 1)

The device package of claim 1, wherein the cold plate is attached to the semiconductor device by direct hybrid bonds.

### Claim 4 (depends on 1)

The device package of claim 1, further comprising a coolant fluid disposed in the coolant channel.

### Claim 5 (depends on 1)

The device package of claim 1, wherein openings in the integrated cooling assembly comprise portions of a fluid path that further comprises the inlet and outlet openings, the openings disposed through the material layer, and the coolant channel.

### Claim 6 (depends on 5)

The device package of claim 5, wherein the openings in the integrated cooling assembly extend between the first side and the second side of the cold plate.

### Claim 7 (depends on 5)

The device package of claim 5, wherein the openings in the integrated cooling assembly comprise gaps between the first side of the cold plate and the semiconductor device.

### Claim 8 (depends on 5)

The device package of claim 5, wherein the first side of the cold plate further comprises a plurality of protruding features that extend downwardly from the base surface to disrupt at least portions of the fluid flow path through the coolant channel.

### Claim 9 (depends on 8)

The device package of claim 8, wherein the protruding features are directly bonded to the semiconductor device.

### Claim 10 (depends on 7)

The device package of claim 7, wherein the gaps are disposed at opposite ends of the base surface.

### Claim 11 (depends on 1)

The device package of claim 1, wherein the package cover comprises one or more coolant line attachment features.

### Claim 12 (depends on 1)

The device package of claim 1, further comprising an underfill layer that at least partially encapsulates the integrated cooling assembly in regions outside of the coolant channel.

### Claim 13 (depends on 1)

The device package of claim 1, wherein the material layer forms an impermeable barrier between the package cover and the cold plate.

### Claim 14 (depends on 1)

The device package of claim 1, wherein side surfaces of the cold plate and the semiconductor device are substantially flush with one another.

### Claim 15 (depends on 1)

The device package of claim 1, wherein:
the semiconductor device is a first semiconductor device and the integrated cooling assembly further comprises a plurality of second semiconductor devices vertically arranged in a device stack; and
the device stack is attached to the first side of the cold plate in a side-by-side arrangement with the first semiconductor device.

### Claim 16 (depends on 15)

The device package of claim 15, wherein the cold plate is attached to the second semiconductor device by direct dielectric bonds.

### Claim 17 (depends on 15)

The device package of claim 15, wherein the cold plate is attached to the second semiconductor device by direct hybrid bonds.

### Claim 18 (depends on 1)

The device package of claim 1, wherein the semiconductor device is a first semiconductor device and the device package further comprises:
a device stack electrically connected to the package substrate in a side-by-side arrangement with the integrated cooling assembly; and
a first TIM layer disposed between the device stack and the package cover.

### Claim 19 (depends on 18)

The device package of claim 18, wherein the package cover comprises a thermally conductive metal that forms a portion of a heat transfer path between the device stack and the coolant channel.

### Claim 20 (depends on 18)

The device package of claim 18, further comprising a heat sink thermally coupled to an outside surface of the package cover, wherein the package cover comprises a thermally conductive metal that forms a portion of a heat transfer path between the device stack and the heat sink.