# US 12,183,655 B2 · Semiconductor device with enhanced thermal dissipation and method for making the same

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- Number: US 12,183,655 B2
- Document ID: US12183655B2
- Status: Granted
- Kind: B2
- Application number: 17/874,274
- Filed: 2022-07-26
- Published: 2022-11-17
- Granted: 2024-12-31
- Earliest claimed: 2018-10-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yang-Che Chen; Chen-Hua Lin; Huang-Wen Tseng; Victor Chiang Liang; Chwen-Ming Liu
- Web page: https://patentgrep.com/patent/US12183655B2

## CPC

- H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)}
- H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/251: {Organics}
- H10W 40/735: {by melting or evaporation of solids}
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07254: {changes in dispositions}
- H10W 72/07255: {changes in materials}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07351: {characterised by changes in properties of the die-attach connectors during connecting}
- H10W 72/07354: {changes in dispositions}
- H10W 72/07355: {changes in materials}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/265: {Providing thermal transfer, e.g. thermal bumps}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/341: {Dispositions of die-attach connectors, e.g. layouts}
- H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/365: {Providing thermal transfer}
- H10W 72/367: {Multiple die-attach connectors having different functions}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9413: {on encapsulations}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ≥50 W/mK.

## Claims

### Claim 1

A semiconductor device, comprising:
a chip disposed over a substrate;
a metal pillar disposed over a main surface of the chip;
a solder layer comprising a solder disposed on the metal pillar;
a lid attached to the chip via the solder layer; and
a thermal interface material layer between the main surface of the chip and the lid,
wherein the solder layer and the thermal interface material layer are different materials,
wherein the substrate, chip, metal pillar, and lid are arranged along a first direction,
wherein the metal pillar extends beyond the main surface of the chip toward the lid in the first direction in a space between the main surface of the chip and the lid, and
wherein the main surface of the chip extends along a second direction perpendicular to the first direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the chip is an integrated fan-out chip, system on a chip, wafer-level chip scale package, or chip on wafer on substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising an underfill layer between the chip and the substrate.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the solder layer has a thermal conductivity of ≥50 W/mK.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a bonding pad between the surface of the chip and the solder layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the metal pillar comprises copper or nickel.

### Claim 7

A semiconductor device, comprising:
a chip disposed over a substrate;
a plurality of bonding pads disposed on a main surface of a chip;
a plurality of metal pillars disposed on respective ones of the plurality of bonding pads, wherein each bonding pad has a pillar disposed thereon;
a solder layer comprising a solder disposed over a surface of each metal pillar;
a lid attached to the chip via the solder layer; and
a thermal interface material layer disposed between each of the plurality of metal pillars and between the main surface of the chip and the lid,
wherein the solder layer and the thermal interface material layer are different materials,
wherein the substrate, chip, metal pillars, and lid are arranged along a first direction,
wherein each of the metal pillars extends beyond the main surface of the chip toward the lid in the first direction in a space between the main surface of the chip and the lid, and
wherein the main surface of the chip extends along a second direction perpendicular to the first direction.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the chip is an integrated fan-out chip, system on a chip, wafer-level chip scale package, or chip on wafer on substrate.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, further comprising an underfill layer between the chip and the substrate.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, further comprising a seed layer between each of the plurality of bonding pads and each of the plurality of pillars.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, wherein the metal pillars comprise aluminum, copper, chromium, iron, manganese, magnesium, molybdenum, nickel, niobium, tantalum, titanium, tungsten, zinc, and alloys thereof.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, wherein the solder layer has a thermal conductivity of ≥50 W/mK.

### Claim 13 (depends on 7)

The semiconductor device of claim 7, wherein the solder is selected from the group consisting of PbSn, AgSn, SnAgCu, CuSnNi, AgCuSbSn, AuSn, and CuSn.

### Claim 14

A semiconductor device, comprising:
a chip disposed over a first main surface of a substrate;
first solder bumps connecting the chip to the first main surface of the substrate;
second solder bumps disposed on a second main surface of the substrate;
conductive vias in the substrate connecting the first solder bumps to the second solder bumps;
a plurality of bonding pads disposed on a first main surface of the chip;
a metal pillar disposed on each of the plurality of bonding pads;
a solder layer disposed over each of the metal pillars;
a thermal interface material disposed between each of the metal pillars, wherein the thermal interface material and the solder layer are formed of different materials; and
a lid in contact with the substrate and attached to the chip via the solder layer and the metal pillars,
wherein the substrate, chip, metal pillars, and lid are arranged along a first direction,
wherein each of the metal pillars extends beyond the main surface of the chip toward the lid in the first direction in a space between the main surface of the chip and the lid, and
wherein the main surface of the chip extends along a second direction perpendicular to the first direction.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the chip is an integrated fan-out chip, system on a chip, wafer-level chip scale package, or chip on wafer on substrate.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, further comprising an underfill layer between the chip and the substrate.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the solder comprises a material having a thermal conductivity of ≥50 W/mK.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein the solder is selected from the group consisting of PbSn, AgSn, SnAgCu, CuSnNi, AgCuSbSn, AuSn, and CuSn.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, wherein the metal pillars comprise aluminum, copper, chromium, iron, manganese, magnesium, molybdenum, nickel, niobium, tantalum, titanium, tungsten, zinc, and alloys thereof.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, further comprising a seed layer between each of the plurality of bonding pads and each of the plurality of pillars.