# US 12,183,652 B2 · Integrated circuit structure

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- Number: US 12,183,652 B2
- Document ID: US12183652B2
- Status: Granted
- Kind: B2
- Application number: 17/884,272
- Filed: 2022-08-09
- Published: 2022-12-01
- Granted: 2024-12-31
- Earliest claimed: 2018-03-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon-Jhy Liaw
- Web page: https://patentgrep.com/patent/US12183652B2

## CPC

- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 48/01: Manufacture or treatment
- H10D 84/853: {comprising FinFETs}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/215: {comprising FinFETs}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An IC structure includes a plurality of first fins, a plurality of second fins, a plurality of first gate structures, a plurality of second gate structures, and a first gate contact. The first fins and the second fins are over a substrate. The first gate structures traverse the plurality of first fins. The second gate structures traverse the plurality of second fins. The first gate structures have a first gate pitch. The second gate structures have a second gate pitch wider than the first gate pitch. The first gate contact is over a first one of the second gate structures. The first gate contact overlaps a location where the first one of the second gate structures traverses across a first one of the second fins.

## Claims

### Claim 1

An integrated circuit (IC) structure, comprising:
a plurality of first fins and a plurality of second fins over a substrate;
a plurality of first gate structures traversing the plurality of first fins;
a plurality of second gate structures traversing the plurality of second fins, the plurality of first gate structures having a first gate pitch, the plurality of second gate structures having a second gate pitch wider than the first gate pitch; and
a first gate contact over a first one of the plurality of second gate structures, the first gate contact overlapping a location where the first one of the plurality of second gate structures traverses across a first one of the plurality of second fins, wherein the first gate contact further overlaps a location where the first one of the plurality of second gate structures traverses across a second one of the plurality of second fins.

### Claim 2 (depends on 1)

The IC structure of claim 1, wherein the first gate contact has an oval profile from a top view.

### Claim 3 (depends on 1)

The IC structure of claim 1, further comprising:
a source/drain contact extending across source/drain regions of the plurality of second fins, the source/drain contact having a longitudinal axis parallel with a longitudinal axis of the first gate contact.

### Claim 4 (depends on 3)

The IC structure of claim 3, wherein the source/drain contact has a different profile than the first gate contact from a top view.

### Claim 5 (depends on 3)

The IC structure of claim 3, wherein the first gate contact is more curved than the source/drain contact from a top view.

### Claim 6 (depends on 3)

The IC structure of claim 3, wherein the first gate contact has a greater length than the source/drain contact from a top view.

### Claim 7 (depends on 1)

The IC structure of claim 1, further comprising:
a second gate contact over a second one of the plurality of second gate structures, the second gate contact overlapping a location where the second one of the plurality of second gate structures traverses across the first one of the plurality of second fins.

### Claim 8 (depends on 7)

The IC structure of claim 7, wherein the second gate contact further overlaps a location where the second one of the plurality of second gate structures traverses across a second one of the plurality of second fins.

### Claim 9 (depends on 1)

The IC structure of claim 1, further comprising:
a gate via overlapping the first gate contact at a fin-free location.

### Claim 10

An IC structure, comprising:
a plurality of semiconductor fins extending along a first direction over a substrate;
a first gate structure extending along a second direction across the plurality of semiconductor fins, the second direction being different from the first direction; and
a first gate contact over the first gate structure, the first gate contact extending along the second direction across the plurality of semiconductor fins.

### Claim 11 (depends on 10)

The IC structure of claim 10, wherein the first gate contact has an elliptical top-view profile.

### Claim 12 (depends on 10)

The IC structure of claim 10, further comprising:
a source/drain contact laterally spaced apart from the first gate structure, the source/drain contact extending along the second direction across the plurality of semiconductor fins.

### Claim 13 (depends on 12)

The IC structure of claim 12, wherein the source/drain contact has a different shape than the first gate contact when viewed in a top view.

### Claim 14 (depends on 10)

The IC structure of claim 10, further comprising:
a second gate structure extending along the second direction across the plurality of semiconductor fins; and
a second gate contact over the second gate structure, the second gate contact extending along the second direction across the plurality of semiconductor fins.

### Claim 15 (depends on 14)

The IC structure of claim 14, wherein the second gate contact has an elliptical top-view profile.

### Claim 16

An IC structure, comprising:
a plurality of semiconductor fins extending along a first direction;
a first gate structure extending along a second direction across the plurality of semiconductor fins, the second direction being non-parallel to the first direction; and
a plurality of first gate vias arranged on the first gate structure in a spaced-apart manner, the plurality of first gate vias respectively overlapping the plurality of semiconductor fins.

### Claim 17 (depends on 16)

The IC structure of claim 16, wherein from a top view, one of the plurality of first gate vias has a largest dimension greater than a fin width of one of the plural semiconductor fins.

### Claim 18 (depends on 16)

The IC structure of claim 16, further comprising:
a second gate structure extending along the second direction across the plurality of semiconductor fins;
a source/drain contact laterally between the first gate structure and the second gate structure; and
a plurality of second gate vias arranged on the second gate structure in a spaced-apart manner, the plurality of second gate vias respectively overlapping the plurality of semiconductor fins.

### Claim 19 (depends on 18)

The IC structure of claim 18, wherein the source/drain contact has a top-view area greater than a top-view area of one of the plurality of first gate vias and the plurality of second gate vias.

### Claim 20 (depends on 1)

The IC structure of claim 1, further comprising:
a gate via over the first gate contact.