# US 12,183,649 B2 · IC package including multi-chip unit with bonded integrated heat spreader

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- Number: US 12,183,649 B2
- Document ID: US12183649B2
- Status: Granted
- Kind: B2
- Application number: 18/222,855
- Filed: 2023-07-17
- Published: 2023-11-09
- Granted: 2024-12-31
- Earliest claimed: 2019-08-01
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Debendra Mallik; Ravindranath Mahajan; Digvijay Raorane
- Web page: https://patentgrep.com/patent/US12183649B2

## CPC

- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/47: by flowing liquids, e.g. forced water cooling
- H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W 40/778: {in encapsulations}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/461: {specially adapted for cooling}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/073: {of die-attach connectors}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/314: {characterized by direct bonding of pads or other interconnections}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

## Claims

### Claim 1

An integrated circuit package, comprising:
a redistribution layer (RDL) structure having a first sidewall and a second sidewall, the second sidewall laterally opposite to the first sidewall;
a first integrated circuit chip on the RDL structure, the first integrated circuit chip comprising a first silicon substrate over an active region, the first silicon substrate having a backside opposite the active region, and the first silicon substrate having a first sidewall and a second sidewall between the active region and the backside, the second sidewall laterally opposite the first sidewall;
a second integrated circuit chip on the RDL structure, the second integrated circuit chip laterally spaced apart from the first integrated circuit chip, the second integrated circuit chip comprising a second silicon substrate over an active region, the second silicon substrate having a backside opposite the active region, and the second silicon substrate having a first sidewall and a second sidewall between the active region and the backside, the second sidewall laterally opposite the first sidewall;
a dielectric material layer laterally between and in contact with the second sidewall of the first silicon substrate and the first sidewall of the second silicon substrate, the dielectric material in contact with the RDL structure;
a back-side bond material over the backside of the first silicon substrate, over the dielectric material layer, and over the backside of the second silicon substrate;
a bond material over the back-side bond material, the bond material separate and distinct from the back-side bond material;
a heat spreader over the bond material, the heat spreader having a first sidewall and a second sidewall, the second sidewall laterally opposite to the first sidewall, wherein the first sidewall of the heat spreader is in vertical alignment with the first sidewall of the RDL structure, and the second sidewall of the heat spreader is in vertical alignment with the second sidewall of the RDL structure; and
a package mold material adjacent to a sidewall of the dielectric material and a sidewall of the RDL structure.

### Claim 2 (depends on 1)

The integrated circuit package of claim 1, wherein the dielectric material is further in contact with the first sidewall of the first silicon substrate and the second sidewall of the second silicon substrate.

### Claim 3 (depends on 1)

Integrated circuit package of claim 1, wherein the dielectric material layer comprises silicon and oxygen.

### Claim 4 (depends on 1)

The integrated circuit package of claim 1, wherein the dielectric material layer has a bulk thermal conductivity less than 5 W/mK.

### Claim 5 (depends on 1)

The integrated circuit package of claim 1, further comprising:
solder features on the RDL structure, the solder features on a side of the RDL structure opposite the first integrated circuit chip and the second integrated circuit chip.

### Claim 6 (depends on 1)

The integrated circuit package of claim 1, wherein the bond material comprises solder.

### Claim 7 (depends on 1)

The integrated circuit package of claim 1, wherein the bond material comprises copper.

### Claim 8 (depends on 1)

The integrated circuit package of claim 1, wherein the bond material comprises gold.

### Claim 9 (depends on 1)

The integrated circuit package of claim 1, wherein the bond material comprises silicon and oxygen.

### Claim 10 (depends on 1)

The integrated circuit package of claim 1, wherein the heat spreader comprises single-crystalline silicon.

### Claim 11

A method of fabricating an integrated circuit package, the method comprising:
coupling a first integrated circuit chip to a redistribution layer (RDL) structure, the RDL structure having a first sidewall and a second sidewall, the second sidewall laterally opposite to the first sidewall, the first integrated circuit chip comprising a first silicon substrate over an active region, the first silicon substrate having a backside opposite the active region, and the first silicon substrate having a first sidewall and a second sidewall between the active region and the backside, the second sidewall laterally opposite the first sidewall;
coupling a second integrated circuit chip to the RDL structure, the second integrated circuit chip laterally spaced apart from the first integrated circuit chip, the second integrated circuit chip comprising a second silicon substrate over an active region, the second silicon substrate having a backside opposite the active region, and the second silicon substrate having a first sidewall and a second sidewall between the active region and the backside, the second sidewall laterally opposite the first sidewall;
forming a dielectric material layer laterally between and in contact with the second sidewall of the first silicon substrate and the first sidewall of the second silicon substrate, the dielectric material in contact with the RDL structure;
forming a back-side bond material over the backside of the first silicon substrate, over the dielectric material layer, and over the backside of the second silicon substrate;
forming a bond material over the back-side bond material, the bond material separate and distinct from the back-side bond material;
coupling a heat spreader to the bond material, the heat spreader having a first sidewall and a second sidewall, the second sidewall laterally opposite to the first sidewall, wherein the first sidewall of the heat spreader is in vertical alignment with the first sidewall of the RDL structure, and the second sidewall of the heat spreader is in vertical alignment with the second sidewall of the RDL structure; and
forming a package mold material adjacent to a sidewall of the dielectric material and a sidewall of the RDL structure.

### Claim 12 (depends on 11)

The method of claim 11, wherein the dielectric material is further in contact with the first sidewall of the first silicon substrate and the second sidewall of the second silicon substrate.

### Claim 13 (depends on 11)

The method of claim 11, wherein the dielectric material layer comprises silicon and oxygen.

### Claim 14 (depends on 11)

The method of claim 11, wherein the dielectric material layer has a bulk thermal conductivity less than 5 W/mK.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
forming solder features on the RDL structure, the solder features on a side of the RDL structure opposite the first integrated circuit chip and the second integrated circuit chip.

### Claim 16 (depends on 11)

The method of claim 11, wherein the bond material comprises solder.

### Claim 17 (depends on 11)

The method of claim 11, wherein the bond material comprises copper.

### Claim 18 (depends on 11)

The method of claim 11, wherein the bond material comprises gold.

### Claim 19 (depends on 11)

The method of claim 11, wherein the bond material comprises silicon and oxygen.

### Claim 20 (depends on 11)

The method of claim 11, wherein the heat spreader comprises single-crystalline silicon.