# US 12,183,648 B2 · Semiconductor device and semiconductor module > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,648 B2 - Document ID: US12183648B2 - Status: Granted - Kind: B2 - Application number: 17/554,043 - Filed: 2021-12-17 - Published: 2022-06-23 - Granted: 2024-12-31 - Earliest claimed: 2020-12-18 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Murata Manufacturing Co., Ltd. - Inventors: Mikiko Fukasawa; Satoshi Goto; Shunji Yoshimi - Web page: https://patentgrep.com/patent/US12183648B2 ## CPC - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H03F 3/195: in integrated circuits - H03F 3/68: Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} - H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H03F 2200/111: the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not - H03F 2200/294: the amplifier being a low noise amplifier [LNA] - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2203/7209: the gated amplifier being switched from a first band to a second band - H10W 44/206: {Wires} - H10W 44/231: {Arrangements for applying bias} - H10W 44/234: {Arrangements for impedance matching} - H10W 44/248: {for antennas} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H03F: AMPLIFIERS ## Abstract In a semiconductor device, when a first surface of a first member is viewed in plan, a plurality of circuit blocks are disposed in an inner region of the first surface. The second member is joined to the first surface of the first member in surface contact with the first surface. The second member includes one or more circuit blocks. A conductive protrusion protrudes from the second member on an opposite side to the first member. One of the circuit blocks in the second member constitutes a first amplifier circuit including a plurality of first transistors that are connected in parallel to each other. At least one of the circuit blocks in the first member overlaps at least one circuit block in the second member in a plan view. ## Claims ### Claim 1 A semiconductor device comprising: a first member having a first surface and including a plurality of circuit blocks disposed in an inner region of the first surface when the first surface is viewed in plan; a second member joined to the first surface of the first member in surface contact with the first surface, the second member including one or more circuit blocks; and a conductive protrusion protruding from the second member on an opposite side to the first member, wherein one of the circuit blocks in the second member constitutes a first amplifier circuit including a plurality of first transistors that are connected in parallel to each other, and at least one of the circuit blocks in the first member overlaps at least one circuit block in the second member in a plan view. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising: a wiring that connects the circuit block in the first member and the circuit block in the second member, the circuit block in the first member and the circuit block in the second member overlapping in a plan view. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the circuit block in the second member overlapping the circuit block in the first member in a plan view constitutes the first amplifier circuit, and the circuit block constituting the first amplifier circuit overlaps one or more of the circuit blocks in the first member in a plan view, the one or more circuit blocks being not operated during operation of the first amplifier circuit. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the circuit block in the first member overlapping the circuit block in the second member in a plan view is a digital circuit, and the first member includes a ground-connected metal film between the circuit block in the first member and the circuit block in the second member which overlap in a plan view. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the second member further includes a second amplifier circuit connected to a stage preceding the first amplifier circuit, and the circuit block in the second member overlapping the circuit block in the first member in a plan view constitutes the first amplifier circuit, and the circuit block constituting the second amplifier circuit does not overlap any of the circuit blocks in the first member in a plan view. ### Claim 6 A semiconductor module comprising: a first member having a first surface and including a plurality of circuit blocks disposed in an inner region of the first surface when the first surface is viewed in plan; a second member joined to the first surface of the first member in surface contact with the first surface, the second member including one or more circuit blocks; a first conductive protrusion protruding from the first surface of the first member; a second conductive protrusion protruding from the second member in a same direction as the first conductive protrusion; and a module substrate on which the first member and the second member are mounted, wherein one of the circuit blocks in the second member constitutes a first amplifier circuit including a plurality of first transistors that are connected in parallel to each other, at least one of the circuit blocks in the first member overlaps at least one circuit block in the second member in a plan view, and the circuit block in the first member and the circuit block in the second member, which overlap in a plan view, are connected to each other via the first conductive protrusion, the second conductive protrusion, and a wiring disposed in or on the module substrate.