# US 12,183,647 B2 · Packaging of a semiconductor device with dual sealing materials

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- Number: US 12,183,647 B2
- Document ID: US12183647B2
- Status: Granted
- Kind: B2
- Application number: 17/196,317
- Filed: 2021-03-09
- Published: 2021-06-24
- Granted: 2024-12-31
- Earliest claimed: 2017-02-28
- Assignees: Mitsubishi Electric Corporation
- Applicants: Mitsubishi Electric Corporation
- Inventors: Soichi Sakamoto; Junji Fujino; Hiroshi Kawashima; Taketoshi Maeda
- Web page: https://patentgrep.com/patent/US12183647B2

## CPC

- H10W 72/00: Interconnections or connectors in packages
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 40/778: {in encapsulations}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/68: Shapes or dispositions thereof
- H10W 72/50: Bond wires
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/40: characterised by their materials
- H10W 76/12: characterised by their shape
- H10W 76/18: Insulating materials, e.g. resins, glasses or ceramics
- H10W 90/00: Package configurations
- H10W 44/234: {Arrangements for impedance matching}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/01315: {Forming coatings}
- H10W 72/01515: {Forming coatings}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07331: {Connecting techniques}
- H10W 72/075: {of bond wires}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 76/10: Containers or parts thereof
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a semiconductor device including an insulating layer, a conductive layer bonded to one main surface of the insulating layer, a semiconductor element arranged such that the upper surface of the semiconductor element faces a direction same as the one main surface of the insulating layer, an upper electrode provided on the upper surface of the semiconductor element, a wiring member that has one end electrically bonded to the upper electrode of the semiconductor element and has another end electrically bonded to the conductive layer, and has a hollow portion, a first sealing material, and a second sealing material, in which the first sealing material seals at least part of the semiconductor element so as to be in contact with the semiconductor element, and the second sealing material seals the wiring member so as to be in contact with the wiring member.

## Claims

### Claim 1

A semiconductor device comprising:
an insulating layer;
a conductive layer bonded to one main surface of the insulating layer;
a semiconductor element arranged such that an upper surface of the semiconductor element faces a direction same as the one main surface of the insulating layer,
an upper electrode provided on the upper surface of the semiconductor element;
a wiring member that has one end electrically bonded to the upper electrode of the semiconductor element and has another end electrically bonded to the conductive layer, and has a hollow portion;
a first sealing material; and
a second sealing material,
wherein
the first sealing material seals at least part of the semiconductor element so as to be in contact with the semiconductor element, the second sealing material seals the wiring member so as to be in contact with the wiring member,
the first sealing material is an epoxy resin, and
the second sealing material is silicone gel,
the semiconductor device further comprising
a heat dissipation plate,
wherein
another main surface of the insulating layer is bonded to one main surface of the heat dissipation plate,
an opening in the insulating layer where the heat dissipation plate is not covered with the insulating layer, the opening having a depth reaching to the heat dissipation plate,
a lower surface of the semiconductor element is bonded to the one main surface of the heat dissipation plate in the opening, the another main surface of the insulating layer being located a distance from the heat dissipation plate that is closer to or equal to a distance from the lower surface of the semiconductor element to the heat dissipation plate,
the first sealing material seals at least part of the semiconductor element and the opening, and
the first sealing material further seals one end of the wiring member, and the second sealing material further seals another end of the wiring member.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the opening is filled with the first sealing material to a height higher than or equal to the one main surface of the insulating layer.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2,
wherein in the opening, the one main surface of the insulating layer is arranged to be higher than the upper surface of the semiconductor element.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2,
wherein a flexural modulus of the second sealing material is smaller than a flexural modulus of the first sealing material.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1,
wherein an area where the wiring member is in contact with the second sealing material is larger than an area where the wiring member is in contact with the first sealing material.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1,
wherein the wiring member is a wire.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein
the insulating layer is glass epoxy.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein
a bonding material that bonds the semiconductor element and the heat dissipation plate is a conductive resin, and
the conductive resin contains one of an epoxy resin, an acrylic resin, and silicone, and a metal filler.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1,
wherein the bonding material that bonds the semiconductor element and the heat dissipation plate is a sinterable bonding material.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1,
wherein a surface of the bonding material that bonds the semiconductor element and the heat dissipation plate is porous.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1,
wherein the semiconductor element is an element that amplifies or switches a high frequency signal.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11,
wherein a material of the semiconductor element is a wide bandgap semiconductor.