# US 12,183,640 B2 · Semiconductor device and methods of formation

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- Number: US 12,183,640 B2
- Document ID: US12183640B2
- Status: Granted
- Kind: B2
- Application number: 17/650,600
- Filed: 2022-02-10
- Published: 2023-08-10
- Granted: 2024-12-31
- Earliest claimed: 2022-02-10
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shahaji B. More
- Web page: https://patentgrep.com/patent/US12183640B2

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/364: {of IGFETs}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/274: {using seed materials}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3452: {Microstructure}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A cladding sidewall layer footing is removed prior to formation of a hybrid fin structure. Removal of the cladding sidewall layer footing prevents a metal gate footing from forming under the hybrid fin structure when the cladding sidewall layer is removed to enable the metal gate to be formed around the nanostructure channels of a nanostructure transistor. Cladding sidewall layers can be formed in an asymmetric manner to include different lengths and/or angles, among other examples. The asymmetric cladding sidewall layers enable asymmetric metal gate structures to be formed for p-type and n-type nanostructure transistors while preventing metal gate footings from forming under hybrid fin structures for p-type and n-type nanostructure transistors. This may reduce a likelihood of short channel effects and leakage within the nanostructure transistors yield of nanostructure transistors formed on a semiconductor substrate.

## Claims

### Claim 1

A method, comprising:
forming a dielectric layer between a first fin structure that is above a semiconductor substrate and a second fin structure that is above the semiconductor substrate and is adjacent to the first fin structure;
removing portions of the dielectric layer to form a shallow trench isolation (STI) region between the first fin structure and the second fin structure and to form a recess above the STI region;
forming, in the recess, a cladding layer over a first sidewall of the first fin structure, over a second sidewall of the second fin structure, and over a top surface of the STI region; and
removing a portion of the cladding layer from the top surface of the STI region to leave a first cladding sidewall layer along the first sidewall and a second cladding sidewall layer along the second sidewall,
wherein the first cladding sidewall layer and the second cladding sidewall layer comprise respective lengths that are asymmetric.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a seed layer over the first sidewall and over the second sidewall prior to forming the cladding layer; and
wherein forming the cladding layer comprises:
forming the cladding layer on the seed layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the seed layer comprises:
forming the seed layer using a chemical vapor deposition process in which a vapor mixture, comprising disilane (Si2H6), is used to deposit the seed layer.

### Claim 4 (depends on 2)

The method of claim 2, wherein forming the seed layer comprises:
forming the seed layer at a first pressure; and
wherein forming the cladding layer comprises:
forming the cladding layer at a second pressure,
wherein the second pressure is lesser relative to the first pressure.

### Claim 5 (depends on 2)

The method of claim 2, wherein forming the seed layer comprises:
forming the seed layer to a thickness in a range from approximately 0.5 nanometers to approximately 1.5 nanometers.

### Claim 6 (depends on 2)

The method of claim 2, wherein forming the seed layer comprises:
forming the seed layer to a first thickness on sides of a plurality of first layers included in the first fin structure and the second fin structure; and
forming the seed layer to a second thickness on sides of a plurality of second layers included in the first fin structure and the second fin structure,
wherein the second thickness is lesser relative to the first thickness.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming a plurality of nanostructures and a plurality of sacrificial nanostructures between the plurality of nanostructures;
removing the plurality of sacrificial nanostructures, the first cladding sidewall layer, and the second cladding sidewall layer; and
forming, after removing the plurality of sacrificial nanostructures, the first cladding sidewall layer, and the second cladding sidewall layer, a gate structure that wraps around each of the plurality of nanostructures.

### Claim 8

A method, comprising:
forming a first fin structure having a first width above a semiconductor substrate;
forming a second fin structure having a second width above the semiconductor substrate;
depositing a dielectric layer between the first fin structure and the second fin structure;
etching a portion of the dielectric layer to form a shallow trench isolation (STI) region between the first fin structure and the second fin structure,
wherein a top surface of the STI region is sloped or slanted as a result of the etching;
forming, in a recess above of the STI region, a cladding layer over a first sidewall of the first fin structure, over a second sidewall of the second fin structure, and over the top surface of the STI region; and
removing a portion of the cladding layer from the top surface of the STI region to leave a first cladding sidewall layer along the first sidewall and a second cladding sidewall layer along the second sidewall.

### Claim 9 (depends on 8)

The method of claim 8, wherein a bottom edge of the first cladding sidewall layer is lower than a bottom edge of the second cladding sidewall layer.

### Claim 10 (depends on 8)

The method of claim 8, wherein a length of the first cladding sidewall layer is greater than a length of the second cladding sidewall layer.

### Claim 11 (depends on 8)

The method of claim 8, wherein the first fin structure is formed to a different height than the second fin structure.

### Claim 12 (depends on 8)

The method of claim 8, wherein the first fin structure is a p-type metal oxide semiconductor (PMOS) fin structure, and wherein the second fin structure is a n-type metal oxide semiconductor (NMOS) fin structure.

### Claim 13 (depends on 8)

The method of claim 8, further comprising:
forming a third fin structure above the semiconductor substrate; and
forming another STI region between the second fin structure and the third fin structure,
wherein a width of the STI region is different from a width of the other STI region.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
forming a third cladding sidewall on a third sidewall associated with the second fin structure and a fourth cladding sidewall on a fourth sidewall associated with the third fin structure,
wherein a length of the third cladding sidewall is different from a length of the fourth cladding sidewall.

### Claim 15

A method, comprising:
forming a plurality of fin structures above a semiconductor substrate;
forming a dielectric layer above the semiconductor substrate and in between the plurality of fin structures;
removing portions of the dielectric layer in between the plurality of fin structures to form at least a first shallow trench isolation (STI) region, a first recess above the first STI region, a second STI region, and a second recess above the second STI region,
wherein a height of the first STI region is greater than a height of the second STI region;
forming a cladding layer over sidewalls of the first recess, over sidewalls of the second recess, over a top surface of the first STI region, and over a top surface of the second STI region; and
removing portions of the cladding layer from the top surface of the first STI region and the top surface of the second STI region to leave a first cladding sidewall layer along a first sidewall of the first recess, a second cladding sidewall layer along a second sidewall of the first recess, a third cladding sidewall layer along a first sidewall of the second recess, and a fourth cladding sidewall along a second sidewall of the second recess.

### Claim 16 (depends on 15)

The method of claim 15, wherein an angle between the first sidewall of the first recess and a bottom edge of the first cladding sidewall layer is greater than an angle between a first sidewall of the second recess and a bottom edge of the third cladding sidewall layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein the first recess has a different width from the second recess.

### Claim 18 (depends on 15)

The method of claim 15, wherein the first STI region and the second STI region are asymmetric.

### Claim 19 (depends on 15)

The method of claim 15, wherein the first cladding sidewall layer and the second cladding sidewall layer include one or more asymmetric properties.

### Claim 20 (depends on 15)

The method of claim 15, wherein a bottom edge of the first cladding sidewall layer is lower than a bottom edge of the second cladding sidewall layer.