# US 12,183,639 B2 · Semiconductor device having deep trench structure and method of manufacturing thereof

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- Number: US 12,183,639 B2
- Document ID: US12183639B2
- Status: Granted
- Kind: B2
- Application number: 18/111,079
- Filed: 2023-02-17
- Published: 2023-06-29
- Granted: 2024-12-31
- Earliest claimed: 2019-04-26
- Assignees: SK keyfoundry Inc.
- Applicants: SK keyfoundry Inc.
- Inventors: Yang Beom Kang; Kang Sup Shin
- Web page: https://patentgrep.com/patent/US12183639B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/0163: {the components including enhancement-mode IGFETs and depletion-mode IGFETs}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/84: Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
- H10P 14/6923: {the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 95/064: {the removal being chemical etching}
- H10P 95/066: {the removal being a selective chemical etching step, e.g. selective dry etching through a mask}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/0148: {comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers}
- H10W 10/021: {of air gaps}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/20: Air gaps
- H10W 20/092: {by smoothing the dielectric parts}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
providing an active region and a shallow trench region on a substrate;
forming a gate electrode on the active region;
forming a first interlayer insulating film on the gate electrode;
forming a deep trench in the substrate;
forming a gap-fill insulating film on the gate electrode and sidewalls of the deep trench to fill the deep trench and seal an opening of the deep trench;
forming a second interlayer insulating film on the gap-fill insulating film, wherein the second interlayer insulating film comprises:
a convex region overlapping the gate electrode; and
a concave region overlapping the deep trench;
selectively removing the convex region of the second interlayer insulating film to reduce a thickness of the second interlayer insulating film overlapping the gate electrode;
forming a third interlayer insulating film on the second interlayer insulating film;
forming a contact plug connected to the active region; and
forming a metal wiring on the contact plug.

### Claim 2 (depends on 1)

The method of claim 1, wherein the selectively removing of the convex region comprises:
forming a blocking pattern on the concave region overlapping the deep trench;
performing an etch-back process on the convex region overlapping the gate electrode; and
removing the blocking pattern.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
performing, after selectively removing the convex region, a chemical mechanical polishing (CMP) of the second interlayer insulating film to form a planarized interlayer insulating film.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
forming an etch stop film on the gate electrode,
wherein the etch stop film and the first interlayer insulating film form a hard mask layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the contact plug is formed through the etch stop film, the first interlayer insulating film, the gap-fill insulating film, the second interlayer insulating film, and the third interlayer insulating film.

### Claim 6 (depends on 1)

The method of claim 1, wherein the deep trench comprises an air gap formed by sealing the opening of the deep trench with the gap-fill insulating film and surrounded by the gap-fill insulating film.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming a sidewall insulating film on the sidewalls of the deep trench,
wherein the gap-fill insulating film is in direct contact with the sidewall insulating film.

### Claim 8

A method of manufacturing a semiconductor device, the method comprising:
providing an active region and an isolation region on a substrate;
forming a gate electrode on the active region;
forming a first interlayer insulating film on the gate electrode;
forming a deep trench through the isolation region on the substrate;
forming a gap-fill insulating film on the gate electrode and sidewalls of the deep trench to fill the deep trench and seal an opening of the deep trench;
forming a second interlayer insulating film on the gap-fill insulating film, the second interlayer insulating film comprising a convex region overlapping the gate electrode and a concave region overlapping the deep trench;
performing an etch-back process on the second interlayer insulating film to selectively remove the convex region of the second interlayer insulating film overlapping the gate electrode;
forming a contact plug connected to the active region; and
forming a metal wiring on the contact plug.

### Claim 9 (depends on 8)

The method of claim 8, wherein the performing of the etch-back process on the second interlayer insulating film comprises:
forming a blocking pattern on the concave region of the second interlayer insulating film overlapping the deep trench; and
performing the etch-back process on the convex region of the second interlayer insulating film using the blocking pattern as a mask pattern; and
removing the blocking pattern.

### Claim 10 (depends on 8)

The method of claim 8, further comprising:
performing a planarization process on the second interlayer insulating film after the performing of the etch-back process on the second interlayer insulating film.

### Claim 11 (depends on 8)

The method of claim 8, further comprising:
depositing a third interlayer insulating film on the second interlayer insulating film,
wherein the contact plug is formed through the first interlayer insulating film, the gap-fill insulating film, the second interlayer insulating film, and the third interlayer cap-insulating film.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
forming a first buried layer on the substrate;
forming a second buried layer on the first buried layer, the first buried layer and the second buried layer having different conductivity types;
forming a drift region and a body region, respectively, on the second buried layer, the drift region and the body region having different conductivity types; and
forming a source region and a drain region in the body region and the drift region, respectively.

### Claim 13

A method of manufacturing a semiconductor device, the method comprising:
providing an active region and an isolation region on a substrate;
forming a gate electrode on the active region;
forming a first interlayer insulating film on the gate electrode;
forming a deep trench through the isolation region on the substrate;
forming a gap-fill insulating film on the gate electrode and sidewalls of the deep trench to fill the deep trench and seal an opening of the deep trench;
forming a second interlayer insulating film on the gap-fill insulating film, the second interlayer insulation film comprising a convex region overlapping the gate electrode and a concave region overlapping the deep trench;
selectively removing the convex region of the second interlayer insulating film by forming a blocking pattern on the concave region of the second interlayer insulating film and performing an etch-back process on the convex region using the blocking pattern as a mask pattern, thereby reducing a thickness of the second interlayer insulating film;
performing a planarization process on the second interlayer insulating film;
forming a contact plug connected to the active region; and
forming a metal wiring on the contact plug.

### Claim 14 (depends on 13)

The method of claim 13, wherein the performing of the planarization process on the second interlayer insulating film comprises:
performing a chemical mechanical polishing (CMP) of the second interlayer insulating film to form a planarized interlayer insulating film.

### Claim 15 (depends on 14)

The method of claim 14, wherein the selectively removing of the convex region first of the second interlayer insulating film overlapping the gate electrode further comprises:
removing the blocking pattern before performing the planarization process.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
forming a third interlayer insulating film on the planarized second interlayer insulating film,
wherein the contact plug is formed through the first interlayer insulating film, the gap-fill insulating film, the second interlayer insulating film, and the third interlayer insulating film.