# US 12,183,638 B2 · In-situ formation of metal gate modulators

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- Number: US 12,183,638 B2
- Document ID: US12183638B2
- Status: Granted
- Kind: B2
- Application number: 18/499,650
- Filed: 2023-11-01
- Published: 2024-02-22
- Granted: 2024-12-31
- Earliest claimed: 2020-05-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsin-Han Tsai; Chung-Chiang Wu; Cheng-Lung Hung; Weng Chang; Chi On Chui
- Web page: https://patentgrep.com/patent/US12183638B2

## CPC

- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/834: {comprising FinFETs}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

## Claims

### Claim 1

An integrated circuit device comprising:
a semiconductor region;
a gate stack comprising:
a gate dielectric over the semiconductor region;
a work-function layer over the gate dielectric;
a silicon layer over the work-function layer, wherein the silicon layer comprises elemental silicon;
a glue layer over and contacting the silicon layer; and
a filling-metal region over and contacting the glue layer; and
a source/drain region aside of the gate stack.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, wherein an interface between the silicon layer and the glue layer is free from oxygen.

### Claim 3 (depends on 1)

The integrated circuit device of claim 1 further comprising a first titanium nitride layer underlying and contacting the silicon layer, wherein the glue layer comprises a second titanium nitride layer contacting the silicon layer.

### Claim 4 (depends on 1)

The integrated circuit device of claim 1, wherein silicon has a peak concentration at an intermediate level between a top surface and a bottom surface of the silicon layer.

### Claim 5 (depends on 4)

The integrated circuit device of claim 4, wherein inside the glue layer, silicon concentrations gradually reduce in a direction pointing from the intermediate level.

### Claim 6 (depends on 1)

The integrated circuit device of claim 1, wherein silicon concentrations have a minimum concentration in the work-function layer.

### Claim 7 (depends on 1)

The integrated circuit device of claim 1, wherein the glue layer has a thickness smaller than about 25 Å.

### Claim 8 (depends on 1)

The integrated circuit device of claim 1, wherein the semiconductor region comprises a semiconductor fin.

### Claim 9 (depends on 1)

The integrated circuit device of claim 1, wherein the work-function layer is an n-work-function layer.

### Claim 10 (depends on 1)

The integrated circuit device of claim 1, wherein silicon has a minimum concentration in the work-function layer.

### Claim 11

A device comprising:
a semiconductor fin;
a high-k dielectric layer on the semiconductor fin;
a work-function layer over the high-k dielectric layer;
a first metal nitride layer over the work-function layer, wherein the first metal nitride layer comprises a first material selected from the group consisting of titanium nitride and tantalum nitride;
a silicon layer over the first metal nitride layer, wherein the silicon layer comprises elemental silicon therein;
a second metal nitride layer over the silicon layer, wherein the second metal nitride layer comprises a second material selected from the group consisting of titanium nitride and tantalum nitride; and
a filling-metal region over and contacting the second metal nitride layer.

### Claim 12 (depends on 11)

The device of claim 11, wherein an interface between the silicon layer and the second metal nitride layer is free from oxygen.

### Claim 13 (depends on 11)

The device of claim 11, wherein silicon has a peak concentration in the silicon layer, and silicon concentrations reduce going into the first metal nitride layer and the second metal nitride layer.

### Claim 14 (depends on 11)

The device of claim 11, wherein the first metal nitride layer is in physical contact with the work-function layer.

### Claim 15 (depends on 11)

The device of claim 11, wherein one of the first metal nitride layer and the second metal nitride layer comprises tantalum nitride.

### Claim 16 (depends on 11)

The device of claim 11, wherein the silicon layer is configured to electrically interconnect the first metal nitride layer and the second metal nitride layer.

### Claim 17

An integrated circuit device comprising:
a semiconductor fin;
a high-k dielectric layer on the semiconductor fin;
a work-function layer over the high-k dielectric layer;
a first metal nitride layer over the work-function layer;
a silicon-containing layer over the first metal nitride layer, wherein a peak concentration of silicon is in the silicon-containing layer;
a second metal nitride layer over the silicon layer, wherein concentrations of the silicon gradually reduce in the first metal nitride layer and the second metal nitride layer and in directions away from the silicon-containing layer; and
a filling-metal region over and contacting the second metal nitride layer.

### Claim 18 (depends on 17)

The integrated circuit device of claim 17, wherein the silicon layer is free from silicon oxide therein.

### Claim 19 (depends on 17)

The integrated circuit device of claim 17, wherein one of the first and the second metal nitride layer comprises tantalum nitride.

### Claim 20 (depends on 17)

The integrated circuit device of claim 17, wherein one of the first and the second metal nitride layer comprises titanium nitride.