# US 12,183,633 B2 · Dielectric cap structure in semiconductor devices and methods of manufacturing the same

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- Number: US 12,183,633 B2
- Document ID: US12183633B2
- Status: Granted
- Kind: B2
- Application number: 17/533,895
- Filed: 2021-11-23
- Published: 2022-10-27
- Granted: 2024-12-31
- Earliest claimed: 2021-04-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Te-Chih Hsiung; Yi-Chen Wang; Guang-Hong Cheng; Wen Wang; Yuan-Tien Tu; Huan-Just Lin
- Web page: https://patentgrep.com/patent/US12183633B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10W 20/42: Vias, e.g. via plugs
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a channel structure, a first gate structure straddling the channel structure, and an epitaxial structure. The epitaxial structure is adjacent to the first gate structure and is coupled to an end of the channel structure. The semiconductor device further includes a first contact structure disposed over and in contact with the epitaxial structure and a nitride-based conformal layer extending at least over the first contact structure. The semiconductor device further includes an oxide-based layer disposed over the nitride-based conformal layer. A portion of the nitride-based conformal layer, disposed over the first contact structure, has a dip that is filled with a first portion of the oxide-based layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a channel structure;
a first gate structure straddling the channel structure;
an epitaxial structure, adjacent the first gate structure, that is coupled to an end of the channel structure;
a first contact structure disposed over and in contact with the epitaxial structure;
a nitride-based conformal layer extending at least over the first contact structure; and
an oxide-based layer disposed over the nitride-based conformal layer;
wherein a first portion of the nitride-based conformal layer, disposed over the first contact structure, has a dip that is filled with a first portion of the oxide-based layer, and
wherein a second portion of the nitride-based conformal layer, extending continuously from the first portion of the nitride-based conformal layer, is disposed over a top surface of the first gate structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a second contact structure disposed over the first gate structure, wherein the second contact structure penetrates through a second portion of the oxide-based layer and the second portion of the nitride-based conformal layer to be in contact with the first gate structure.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a gate spacer interposed between the first contact structure and the first gate structure, wherein the second contact structure and the nitride-based conformal layer directly contact the first gate spacer.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, further comprising a gate spacer interposed between the first contact structure and the first gate structure, wherein the second contact structure is separated apart from the gate spacer with the nitride-based conformal layer and the second portion of the oxide-based layer.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, further comprising a third contact structure disposed over the first contact structure, wherein the third contact structure penetrates through the first portion of the oxide-based layer and the nitride-based conformal layer to be in contact with the first contact structure.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising an etch stop layer disposed over the oxide-based layer and the nitride-based conformal layer, wherein the second and third contact structures further penetrate through the etch stop layer, respectively.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the etch stop layer has a top surface and a bottom surface, and wherein a portion of the top surface and a portion of the bottom surface that are disposed above a second gate structure each have a dip.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the channel structure includes a plurality of nanostructures vertically spaced apart from one another.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first gate structure wraps around each of the plurality of nanostructures.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the channel structure contains a fin structure that is integrally formed from a substrate.

### Claim 11

A semiconductor device, comprising:
a channel structure;
a first gate structure straddling the channel structure;
a source/drain structure, adjacent the first gate structure, that is coupled to an end of the channel structure;
a first contact structure disposed over and in contact with the source/drain structure;
a gate spacer disposed between the first gate structure and the first contact structure;
a nitride-based conformal layer extending over the first contact structure, the gate spacer, and at least a portion of the first gate structure;
an oxide-based layer disposed over the nitride-based conformal layer; and
a second contact structure that penetrates through a first portion of the oxide-based layer and the nitride-based conformal layer to be in contact with the first gate structure, wherein the first portion of the oxide-based layer extends to below a top surface the nitride-based conformal layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein a portion of the nitride-based conformal layer, disposed over the first contact structure, has a dip that is filled with a second portion of the oxide-based layer.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, further comprising an etch stop layer disposed over the oxide-based layer and the nitride-based conformal layer, wherein the second contact structure further penetrates through the etch stop layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the etch stop layer has a top surface and a bottom surface, and wherein a portion of the top surface and a portion of the bottom surface that are disposed above a second gate structure each have a dip.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the nitride-based conformal layer also extends over the second gate structure.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein the channel structure includes a plurality of nanostructures vertically spaced apart from one another.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the first gate structure wraps around each of the plurality of nanostructures.

### Claim 18

A method for making semiconductor devices, comprising:
forming a semiconductor device that at least includes a gate structure straddling a channel structure and a first epitaxial structure adjacent the gate structure, wherein the first epitaxial structure is overlaid by an interlayer dielectric;
forming a nitride-based conformal layer that extends over the gate structure and the interlayer dielectric;
forming an oxide-based layer over the nitride-based conformal layer, wherein the oxide-based layer includes a first portion that fills up a recess above the gate structure; and
forming a first contact structure that extends through the first portion of the oxide-based layer and the nitride-based conformal layer to couple to the gate structure.

### Claim 19 (depends on 18)

The method of claim 18, further comprising forming an etch stop layer over the oxide-based layer, wherein the first contact structure further extends through the etch stop layer.

### Claim 20 (depends on 18)

The method of claim 18, wherein the semiconductor device further includes a second epitaxial structure opposite the gate structure from the first epitaxial structure, the method further comprises:
prior to the step of forming the nitride-based conformal layer, forming a second contact structure coupled to the second epitaxial structure, wherein a portion of nitride-based layer, disposed over the second contact structure, has a dip that is filled with a second portion of the oxide-based layer.