# US 12,183,631 B2 · Methods for copper doped hybrid metallization for line and via

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- Number: US 12,183,631 B2
- Document ID: US12183631B2
- Status: Granted
- Kind: B2
- Application number: 17/839,817
- Filed: 2022-06-14
- Published: 2023-01-05
- Granted: 2024-12-31
- Earliest claimed: 2021-07-02
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Suketu Parikh; Alexander Jansen; Joung Joo Lee; Lequn Liu
- Web page: https://patentgrep.com/patent/US12183631B2

## CPC

- H10P 72/0461: {characterised by the presence of two or more transfer chambers}
- H10W 20/059: {by reflowing or applying pressure}
- H10P 70/234: {the processing being the formation of vias or contact holes}
- H10P 95/062: {involving a dielectric removal step}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/034: {bottomless barrier, adhesion or liner layers}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/049: {by diffusing alloying elements}
- H10W 20/0552: {by diffusing metallic dopants to react with dielectrics}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/084: {for dual-damascene structures}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4424: {Copper alloys}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.

## Claims

### Claim 1

A method of forming an interconnect, comprising:
depositing a first copper layer with a dopant with a first dopant content on a feature on a substrate by sputtering a first copper-based target at a first temperature;
annealing the substrate at a second temperature to reflow the first copper layer on the substrate to migrate the dopant in the first copper layer towards a dielectric interface;
depositing a second copper layer with the dopant with a second dopant content by sputtering a second copper-based target at the first temperature, wherein the second dopant content is less than the first dopant content; and
annealing the substrate at a third temperature to reflow the second copper layer on the substrate to fill the feature and form at least a portion of the interconnect, wherein the third temperature is less than or equal to the second temperature.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first dopant content is approximately 0.5 percent to approximately 10 percent or wherein the second dopant content is zero percent to approximately 0.5 percent.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first temperature is zero degrees Celsius to approximately 200 degrees Celsius, wherein the second temperature is approximately 200 degrees Celsius to approximately 400 degrees Celsius, or wherein the third temperature is approximately 200 degrees Celsius to approximately 400 degrees Celsius.

### Claim 4 (depends on 1)

The method of claim 1, wherein the dopant is manganese, magnesium, cobalt, graphene, or aluminum.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
prior to deposition of the first copper layer:
etching an etch stop layer in a bottom of a via to expose a portion of an underlying metallic layer;
degassing and precleaning the substrate on the substrate;
selectively depositing a barrier layer on sidewalls of the via in interconnect structures; and
conformally depositing a liner layer on the portion of the underlying metallic layer on the bottom of the via and on the barrier layer on the sidewalls of the via in the interconnect structures.

### Claim 6 (depends on 5)

The method of claim 5 performed without a vacuum break.

### Claim 7 (depends on 5)

The method of claim 5, wherein the barrier layer is formed from tantalum nitride and the liner layer is formed from cobalt or ruthenium.

### Claim 8 (depends on 1)

The method of claim 1, wherein the substrate is lifted above a pedestal to decrease the third temperature to a value less than the second temperature when annealing the second copper layer to make the second copper layer graded.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
etching back a portion of the first copper layer with a dry SiOC etch after annealing and prior to depositing the second copper layer to form the second copper layer with a greater cross-section for reduced interconnect resistivity.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
performing a chemical mechanical polishing process on the substrate after deposition and annealing of the second copper layer.

### Claim 11 (depends on 1)

The method of claim 1, wherein the depositing of the first copper layer and the annealing of the substrate at the second temperature is a first cyclic process that is performed more than once or wherein the depositing of the second copper layer and the annealing of the substrate at the third temperature is a second cyclic process that is performed more than once.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
directionally depositing the first copper layer with the dopant with the first dopant content on the substrate, wherein the feature is at least one damascene structure including at least one via and at least one trench; and
annealing the substrate at a second temperature to reflow the first copper layer on the substrate to migrate the dopant in the first copper layer towards the dielectric interface, wherein the at least one via of the damascene structure is completely filled and the at least one trench on the substrate has a portion of the first copper layer on at least one sidewall.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first dopant content is approximately 0.5 percent to approximately 10 percent and wherein the second dopant content is zero percent to approximately 0.5 percent.

### Claim 14

A method of forming an interconnect, comprising:
depositing a first copper layer with a dopant with a first dopant content on at least one trench on a substrate by sputtering a first copper-based target at a first temperature;
annealing the substrate at a second temperature to migrate the dopant in the first copper layer to a sidewall of the at least one trench and to migrate the dopant in the first copper layer into a barrier layer of the at least one trench;
depositing a second copper layer with the dopant with a second dopant content on the at least one trench by sputtering a second copper-based target at the first temperature, wherein the second dopant content is less than the first dopant content; and
annealing the substrate at a third temperature to reflow the second copper layer on the substrate to fill the at least one trench, wherein the third temperature is less than or equal to the second temperature.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first dopant content is approximately 0.5 percent to approximately 10 percent and wherein the second dopant content is zero percent to approximately 0.5 percent.

### Claim 16 (depends on 14)

The method of claim 14, wherein the first temperature is zero degrees Celsius to approximately 200 degrees Celsius, wherein the second temperature is approximately 200 degrees Celsius to approximately 400 degrees Celsius, and wherein the third temperature is approximately 200 degrees Celsius to approximately 400 degrees Celsius.

### Claim 17

A method of forming an interconnect, comprising:
depositing a metal layer on at least one trench on a substrate by sputtering a metal-based target at a first temperature;
annealing the substrate at a second temperature to reflow the metal layer in the at least one trench and fill at least one via in the at least one trench to improve electro migration of the at least one via and sidewalls of the at least one trench;
etching back the metal layer on the sidewalls of the at least one trench with an isotropic metal etch to allow for additional bulk fill to reduce resistivity of the at least one trench;
depositing a copper layer with a dopant with a dopant content on the at least one trench by sputtering a copper-based target at the first temperature; and
annealing the substrate at a third temperature to reflow the copper layer on the substrate to fill the at least one trench, wherein the third temperature is less than or equal to the second temperature.

### Claim 18 (depends on 17)

The method of claim 17, wherein the isotropic metal etch uses nitrogen trifluoride gas with oxygen gas or chlorine gas with oxygen gas to etch the metal layer.

### Claim 19 (depends on 17)

The method of claim 17, wherein the metal layer is cobalt, ruthenium, tungsten, molybdenum, or copper alloy with a dopant of manganese or wherein the dopant content is zero percent to approximately 0.5 percent.

### Claim 20 (depends on 17)

The method of claim 17, wherein the first temperature is zero degrees Celsius to approximately 200 degrees Celsius, wherein the second temperature is approximately 200 degrees Celsius to approximately 400 degrees Celsius, and wherein the third temperature is approximately 200 degrees Celsius to approximately 400 degrees Celsius.
