# US 12,183,630 B2 · Additive interconnect formation

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,183,630 B2
- Document ID: US12183630B2
- Status: Granted
- Kind: B2
- Application number: 17/691,085
- Filed: 2022-03-09
- Published: 2023-09-14
- Granted: 2024-12-31
- Earliest claimed: 2022-03-09
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ashim Dutta; Ekmini Anuja De Silva; Chih-Chao Yang; Jennifer Church
- Web page: https://patentgrep.com/patent/US12183630B2

## CPC

- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10W 20/0636: {the conductive members being on sidewalls}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/071: {of dielectric parts thereof}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/46: comprising air gaps
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor substrate has a metal via in the substrate, and has, on the substrate, a metal line that is less than 8 nanometers (nm) wide and at least 20 nm tall. A method for making a semiconductor structure includes forming a metal via in a substrate; forming a mandrel atop and offset from the via; depositing a metal-containing liner onto the mandrel; exposing the top of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and growing a metal line on each portion of the liner.

## Claims

### Claim 1

A method for making a semiconductor structure, the method comprising:
forming a metal via in a substrate;
forming a mandrel in contact with a top surface of the via and offset from the via;
depositing a metal-containing liner onto the mandrel;
exposing a top portion of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and
growing a metal line on each portion of the liner.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming the mandrel to a height of at least 20 nm.

### Claim 3 (depends on 2)

The method of claim 2, further comprising forming multiple mandrels, liners, and lines, then filling a dielectric material between the lines at opposing sides of adjacent mandrels.

### Claim 4 (depends on 3)

The method of claim 3, wherein the mandrel comprises a semiconductor, further comprising replacing the mandrel with additional dielectric material.

### Claim 5 (depends on 2)

The method of claim 2, further comprising depositing the liner by atomic layer deposition.

### Claim 6 (depends on 2)

The method of claim 2, wherein the liner is deposited to no more than 3 nm thickness.

### Claim 7 (depends on 2)

The method of claim 2, further comprising growing the line by selective deposition.

### Claim 8 (depends on 2)

The method of claim 2, wherein the line is grown to no more than 8 nm thickness.

### Claim 9 (depends on 8)

The method of claim 8, wherein the line is grown to a surface roughness less than 1 nm.

### Claim 10 (depends on 2)

The method of claim 2, wherein the liner comprises at least one of titanium, tantalum, tungsten, and ruthenium.

### Claim 11 (depends on 10)

The method of claim 10, wherein the line comprises at least one of ruthenium, cobalt, and tungsten.

### Claim 12 (depends on 11)

The method of claim 11, wherein the line comprises cobalt.

### Claim 13 (depends on 11)

The method of claim 11, wherein the line comprises ruthenium.

### Claim 14 (depends on 10)

The method of claim 10, wherein the liner comprises ruthenium.

### Claim 15 (depends on 4)

The method of claim 4, wherein the additional dielectric is atop and in contact with a portion of the via and wherein the additional dielectric comprises a void.

### Claim 16 (depends on 4)

The method of claim 4, wherein the additional dielectric comprises a low-k material.

### Claim 17 (depends on 4)

The method of claim 4, wherein the additional dielectric is co-planar with the liner and the line.

### Claim 18 (depends on 1)

The method of claim 1, wherein the mandrel comprises a dielectric material.

### Claim 19 (depends on 1)

The method of claim 1, wherein a combined width of the line and the liner is less than the width of the via.

### Claim 20 (depends on 1)

The method of claim 1, wherein a combined width of the line and the liner is less than 8 nanometers (nm), with less than 1 nm line width roughness; and
wherein depositing the metal-containing liner is by atomic layer deposition.