# US 12,183,628 B2 · Integrated circuit and method for manufacturing the same

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- Number: US 12,183,628 B2
- Document ID: US12183628B2
- Status: Granted
- Kind: B2
- Application number: 17/818,115
- Filed: 2022-08-08
- Published: 2022-12-01
- Granted: 2024-12-31
- Earliest claimed: 2020-10-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Kuan-Wei Huang; Yi-Nien Su; Yu-Yu Chen; Jyu-Horng Shieh
- Web page: https://patentgrep.com/patent/US12183628B2

## CPC

- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10P 52/402: {of semiconductor materials}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/076: {in via holes or trenches}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/46: comprising air gaps
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a dielectric layer over a substrate;
a conductive feature over the substrate and surrounded by the dielectric layer;
an insulating protection layer between sidewalls of the conductive feature and the dielectric layer;
a conductive cap layer over the conductive feature; and
a void sealed within the dielectric layer and adjacent to the conductive feature,
wherein an upper surface of the dielectric layer is substantially flushed with an upper surface of the conductive feature.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a barrier layer disposed between the conductive feature and the insulating protection layer.

### Claim 3 (depends on 2)

The integrated circuit structure of claim 2, wherein a bottom of the conductive feature is free of the insulating protection layer.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, further comprising an etch stop layer disposed over conductive feature, the dielectric layer and the void.

### Claim 5 (depends on 4)

The integrated circuit structure of claim 4, further comprising:
an inter-metal dielectric (IMD) on the etch stop layer; and
a conductive via in the IMD and the etch stop layer, and electrically connected to the conductive feature.

### Claim 6 (depends on 5)

The integrated circuit structure of claim 5, wherein a bottom surface of the conductive via is in contact with the conductive cap layer.

### Claim 7 (depends on 1)

The integrated circuit structure of claim 1, wherein the dielectric layer comprises a lower dielectric layer and an upper dielectric layer stacked on the lower dielectric layer.

### Claim 8 (depends on 7)

The integrated circuit structure of claim 7, wherein the void is entirely sealed within the upper dielectric layer.

### Claim 9 (depends on 1)

The integrated circuit structure of claim 1, further comprising an electrical terminal disposed under and electrically connected to the conductive feature.

### Claim 10

A method for fabricating an integrated circuit structure, comprising:
forming a first opening in a dummy layer over a substrate;
forming a conductive feature in the first opening;
forming a first cap layer on the conductive feature, wherein portions of the dummy layer are exposed through the first cap layer;
removing the dummy layer entirely to form a second opening over the substrate;
filling the second opening with a dielectric layer, wherein a void is sealed within the dielectric layer; and
removing the first cap layer, a top portion of the conductive feature and a top portion of the dielectric layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a protection layer along sidewalls of the first opening; and
forming a barrier layer in the first opening prior to the forming of the conductive feature.

### Claim 12 (depends on 10)

The method of claim 10, further comprising forming a second cap layer on the conductive feature subsequent to the removing of the first cap layers, the top portion of the conductive feature and the top portion of the dielectric layer.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
forming an etch stop layer on the second cap layer and the dielectric layer;
forming an inter-metal dielectric (IMD) on the etch stop layer;
etching the IMD to form a via hole in the IMD; and
forming a conductive via in the via hole.

### Claim 14 (depends on 13)

The method of claim 13, wherein the second cap layer is in contact with the conductive via.

### Claim 15

A method for fabricating an integrated circuit structure, comprising:
receiving a substrate comprising a first dielectric layer and a second dielectric layer over the first dielectric layer;
forming a first opening in the first dielectric layer and the second dielectric layer;
forming a conductive feature in the first opening;
removing the second dielectric layer to form a second opening over the substrate;
forming a third dielectric layer covering the conductive feature and filling in the second opening with a void entirely sealed within;
removing a top portion of the conductive feature and a top portion of the third dielectric layer; and
forming an etch stop layer over the conductive feature and the third dielectric layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first dielectric layer is exposed through a bottom of the second opening.

### Claim 17 (depends on 15)

The method of claim 15, further comprising forming a protection layer along sidewalls of the first opening.

### Claim 18 (depends on 17)

The method of claim 17, further comprising forming a barrier layer over the protection layer prior to the forming of the conductive feature.

### Claim 19 (depends on 15)

The method of claim 15, further comprising forming a cap layer on the conductive feature subsequent to the removing of the top portion of the conductive feature and the top portion of the dielectric layer.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
forming an inter-metal dielectric (IMD) on the etch stop layer;
etching the IMD to form a via hole; and
forming a conductive via in the vial hole.