# US 12,183,623 B2 · Semiconductor devices and methods for fabricating the same

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- Number: US 12,183,623 B2
- Document ID: US12183623B2
- Status: Granted
- Kind: B2
- Application number: 17/709,371
- Filed: 2022-03-30
- Published: 2023-03-02
- Granted: 2024-12-31
- Earliest claimed: 2021-08-31
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Huidan Hou; Lan Yao; Yanwei Shi
- Web page: https://patentgrep.com/patent/US12183623B2

## CPC

- H10B 41/49: comprising different types of peripheral transistor
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/40: characterised by the peripheral circuit region
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device and a method for fabricating the same are disclosed. A substrate including a first device region and a second device region is provided. A first isolation structure is formed in the substrate of the first device region and a second isolation structure is formed in the substrate of the second device region. Ion implantation on the first isolation structure is performed. The first isolation structure and the second isolation structure are etched back to form a first recess in the first isolation structure and a second recess in the second isolation structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a first isolation structure corresponding to a first device region of a substrate and comprising a first insulating layer in a first isolation groove of the first isolation structure;
a second isolation structure corresponding to a second device region of the substrate and comprising a second insulating layer in a second isolation groove of the second isolation structure;
a first gate structure arranged on sidewalls of the first isolation groove and comprising a first gate oxide layer and a first gate layer; and
a second gate structure arranged on sidewalls of the second isolation groove and comprising a second gate oxide layer and a second gate layer,
wherein:
a depth of the first gate structure in a longitudinal direction, perpendicular to a lateral direction of the substrate, is greater than a depth of the second gate structure in the longitudinal direction; and
the first gate layer is discontinuous in the first isolation groove.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
a depth of the first isolation groove in the longitudinal direction is greater than the depth of the second isolation groove in the longitudinal direction.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein:
the depth of the first isolation groove is approximately 4500 Å to approximately 4700 Å; and
the depth of the second isolation groove is approximately 3100 Å to approximately 3300 Å.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein:
an area of the first gate oxide layer on the sidewalls of the first isolation groove is greater than an area of the second gate oxide layer on the sidewalls of the second isolation groove.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein:
the first gate oxide layer is further arranged on the substrate of the first device region, and the second gate oxide layer is further arranged on the substrate of the second device region, a thickness of the first gate oxide layer on the substrate of the first device region being greater than a thickness of the second gate oxide layer on the substrate of the second device region.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein:
the first gate layer is further arranged on a surface of the first gate oxide layer on the substrate; and
the second gate layer is further arranged on a surface of the second gate oxide layer on the substrate.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein:
a first insulating layer is arranged in the first isolation groove, the first gate oxide layer and the first gate layer on the sidewalls of the first isolation groove being arranged between the substrate and the first insulating layer; and
a second insulating layer is arranged in the second isolation groove, the second gate oxide layer and the second gate layer on the sidewalls of the second isolation groove being arranged between the substrate and the second insulating layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein:
a first insulating material is inserted into and between the first gate layer over the first insulating layer to separate the first gate layer into two parts in the first isolation groove.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein:
the first insulating material is in contact with the first insulating layer in the first isolation groove.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first insulating material inserted into and arranged between the first gate layer over the first insulating layer, the first insulating material being configured to separate the first gate layer into two parts in the first isolation groove; and
a second insulating material inserted into and arranged between the second gate layer over the second insulating layer, the second insulating material being configured to separate the second gate layer into two parts in the second isolation groove.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein:
in the longitudinal direction, a length of the first insulating material is greater than a length of the second insulating material.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein:
a bottom of the first insulating layer in the first isolation groove is lower than a bottom of the second insulating layer in the second isolation groove, in the longitudinal direction.

### Claim 13

A semiconductor device, comprising:
a first semiconductor device arranged in a first region of a substrate and comprising a first insulating layer in a first isolation groove of the substrate and a first gate structure over the first insulating layer, wherein the first gate structure comprises:
a first gate oxide layer arranged over sidewalls of the first isolation groove;
a first gate layer arranged over the first gate oxide layer; and
a first insulating material arranged over the first insulating layer and inserted between the first gate layer; and
a second semiconductor device arranged in a second region of the substrate and comprising a second insulating layer in a second isolation groove of the substrate and a second gate structure over the second insulating layer, wherein the second gate structure comprises:
a second gate oxide layer arranged over sidewalls of the second isolation groove;
a second gate layer arranged over the second gate oxide layer; and
a second insulating material arranged over the second insulating layer and inserted between the second gate layer,
wherein:
the first insulating material is identical to the second insulating material; and
a thickness of the first gate oxide layer is greater than a thickness of the second gate oxide layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein:
in a longitudinal direction perpendicular to a lateral direction of the substrate, a bottom of the first insulating layer in the first isolation groove is lower than a bottom of the second insulating layer in the second isolation groove.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein:
an area of the first gate oxide layer over the sidewalls of the first isolation groove is greater than an area of the second gate oxide layer over the sidewalls of the second isolation groove.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein:
in a longitudinal direction perpendicular to a lateral direction of the substrate, a length of the first insulating material is greater than a length of the second insulating material.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, wherein:
the first insulating material is configured to separate the first gate layer into two parts in the first isolation groove; and
the second insulating material is configured to separate the second gate layer into two parts in the second isolation groove.

### Claim 18

A semiconductor device, comprising:
a first semiconductor device arranged in a first region of a substrate and comprising a first insulating layer in a first isolation groove of the substrate and a first gate structure over the first insulating layer, wherein the first gate structure comprises:
a first gate oxide layer arranged over sidewalls of the first isolation groove; and
a first gate layer arranged over the first gate oxide layer; and
a second semiconductor device arranged in a second region of the substrate and comprising a second insulating layer in a second isolation groove of the substrate and a second gate structure over the second insulating layer, wherein the second gate structure comprises:
a second gate oxide layer arranged over sidewalls of the second isolation groove; and
a second gate layer arranged over the second gate oxide layer,
wherein:
a bottom of the first insulating layer in the first isolation groove is lower than a bottom of the second insulating layer in the second isolation groove in a longitudinal direction perpendicular to a lateral direction of the substrate.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, further comprising:
a first insulating material arranged over the first insulating layer and inserted between the first gate layer.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein:
the first insulating material is in contact with the first insulating layer in the first isolation groove.