# US 12,183,596 B2 · Low cost package warpage solution

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- Number: US 12,183,596 B2
- Document ID: US12183596B2
- Status: Granted
- Kind: B2
- Application number: 18/226,129
- Filed: 2023-07-25
- Published: 2023-11-16
- Granted: 2024-12-31
- Earliest claimed: 2014-12-18
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Omkar G. Karhade; Nitin A. Deshpande; Debendra Mallik; Bassam M. Ziadeh; Yoshihiro Tomita
- Web page: https://patentgrep.com/patent/US12183596B2

## CPC

- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 90/00: Package configurations
- H10W 72/01271: {Cleaning, e.g. oxide removal or de-smearing}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07202: {using auxiliary members}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07234: {Using a reflow oven}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/387: {Flow barriers}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

## Claims

### Claim 1

A semiconductor package, comprising:
a substrate having a conductive trace thereon;
a device die attached to the substrate, the device die having a first side and a second side, the second side opposite the first side;
a reinforcement layer coupled to the substrate, the reinforcement layer laterally spaced apart from the first side of the device die, wherein the conductive trace extends from a first location beneath the device die to a location beneath the reinforcement layer; and
an adhesive layer between the reinforcement layer and the substrate.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the device die is electrically coupled to the conductive trace by a solder bump.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the reinforcement layer comprises stainless steel.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the adhesive layer comprises an epoxy.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the substrate comprises a solder resist over the conductive trace.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the reinforcement layer has a substantially square outer perimeter.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein the reinforcement layer has a substantially square opening.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the reinforcement layer has a rectangular opening.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the reinforcement layer has a substantially square opening.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein the reinforcement layer has a thickness in a range between 100 microns and 1 mm.

### Claim 11 (depends on 1)

The semiconductor package of claim 1, wherein the reinforcement layer has a thickness greater than a thickness of the device die.

### Claim 12

A computing device, comprising:
a board; and
a semiconductor package coupled to the board, the semiconductor package, comprising:
a substrate having a conductive trace thereon;
a device die attached to the substrate, the device die having a first side and a second side, the second side opposite the first side;
a reinforcement layer coupled to the substrate, the reinforcement layer laterally spaced apart from the first side of the device die, wherein the conductive trace extends from a first location beneath the device die to a location beneath the reinforcement layer; and
an adhesive layer between the reinforcement layer and the substrate.

### Claim 13 (depends on 12)

The computing device of claim 12, further comprising:
a memory die coupled to the board.

### Claim 14 (depends on 12)

The computing device of claim 12, further comprising:
a communication chip coupled to the board.

### Claim 15 (depends on 12)

The computing device of claim 12, further comprising:
a battery coupled to the board.

### Claim 16 (depends on 12)

The computing device of claim 12, further comprising:
a speaker coupled to the board.

### Claim 17 (depends on 12)

The computing device of claim 12, further comprising:
a GPS coupled to the board.

### Claim 18 (depends on 12)

The computing device of claim 12, further comprising:
a camera coupled to the board.