# US 12,183,594 B2 · Semiconductor device with tiered pillar and manufacturing method thereof

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- Number: US 12,183,594 B2
- Document ID: US12183594B2
- Status: Granted
- Kind: B2
- Application number: 17/340,298
- Filed: 2021-06-07
- Published: 2021-09-23
- Granted: 2024-12-31
- Earliest claimed: 2017-03-23
- Assignees: Amkor Technology Singapore Holding Pte. Ltd.
- Applicants: Amkor Technology Singapore Holding Pte. Ltd.
- Inventors: Ronald Patrick Huemoeller; Michael G. Kelly; Curtis Zwenger
- Web page: https://patentgrep.com/patent/US12183594B2

## CPC

- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/01: Manufacture or treatment
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/016: {using moulds}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07235: {Applying EM radiation, e.g. induction heating or using a laser}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.

## Claims

### Claim 1

A semiconductor device, comprising:
a redistribution structure comprising a redistribution structure top side, a redistribution structure bottom side, and one or more conductive layers between the redistribution structure top side and the redistribution structure bottom side, the redistribution structure top side comprising top side conductive pads coupled to the one or more conductive layers;
a semiconductor die comprising a die top side and a die bottom side, the die bottom side coupled to first conductive pads of the top side conductive pads;
a conductive structure comprising an upper tier and a lower tier, wherein the lower tier comprises a lower tier upper end, a lower tier lower end, and a lower tier sidewall between the lower tier upper end and the lower tier lower end, wherein the lower tier lower end is coupled to a second conductive pad of the top side conductive pads, wherein the upper tier comprises an upper tier upper end, an upper tier lower end, and an upper tier sidewall between the upper tier upper end and the upper tier lower end, and wherein the upper tier lower end is coupled to the lower tier upper end; and
an encapsulant comprising an encapsulant top side and an encapsulant bottom side, wherein the encapsulant encapsulates at least a portion of the semiconductor die and at least a portion of the redistribution structure top side, wherein the encapsulant is contacts the lower tier sidewall and the upper tier sidewall, and wherein the encapsulant top side does not cover the upper tier upper end.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
the lower tier has a first width; and
the upper tier has a second width that is smaller than the first width.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein:
the lower tier has a first width; and
the upper tier has a second width that is larger than the first width.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a longitudinal axis of the upper tier is aligned with a longitudinal axis of the lower tier.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a longitudinal axis of the upper tier is not aligned with a longitudinal axis of the lower tier.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, comprising a stepped transition between the lower tier upper end and the upper tier lower end.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein:
the lower tier upper end has a first width; and
the lower tier lower end has a second width that is smaller than the first width.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein:
the upper tier upper end has a third width; and
the upper tier lower end has a fourth width that is larger than the third width.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein:
the upper tier upper end has a third width; and
the upper tier lower end has a fourth width that is smaller than the third width.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein:
the lower tier comprises a lower frustum of the conductive structure;
the upper tier comprises an upper frustum of the conductive structure;
the lower frustum comprises a base surface coupled to the second conductive pad of the redistribution structure; and
the upper frustum comprises a base surface coupled to a top surface of the lower frustum.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein:
a horizontal cross section of the lower tier is circular; and
a horizontal cross section of the upper tier is circular.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein:
a horizontal cross section of the lower tier is non-circular; and
a horizontal cross section of the upper tier is non-circular.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein:
a horizontal cross section of the lower tier has a first shape; and
a horizontal cross section of the upper tier is a second shape that is different from the first shape.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the encapsulant extends between the die bottom side and the redistribution structure top side.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, comprising:
an underfill that extends between the die bottom side and the redistribution structure top side; and
wherein the encapsulant contacts the underfill.

### Claim 16 (depends on 1)

The semiconductor device of claim 1, comprising another redistribution structure over the encapsulant top side and coupled to the upper tier upper end.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, wherein a height of the lower tier upper end from the redistribution structure top side is greater than a height of the die bottom side from the redistribution structure top side.

### Claim 18

A method of forming a semiconductor device, the method comprising:
providing a redistribution structure comprising a redistribution structure top side, a redistribution structure bottom side, and one or more conductive layers between the redistribution structure top side and the redistribution structure bottom side, the redistribution structure top side comprising top side conductive pads coupled to the one or more conductive layers;
coupling a die bottom side of a semiconductor die to first conductive pads of the top side conductive pads;
forming a conductive structure comprising a conductive structure lower end coupled to a second conductive pad of the top side conductive pads, the forming comprising:
forming a first layer over the redistribution structure top side;
forming a second layer over the first layer;
forming a first hole through the first layer;
forming a second hole through the second layer such that the second hole adjoins the first hole;
filling the first hole with conductive material to form a first tier; and
filling the second hole with conductive material to form a second tier; and
encapsulating the semiconductor die, the first tier, and the second tier with an encapsulant such that the encapsulant conforms to a sidewall of the first tier, a sidewall of the second tier, and a sidewall of the semiconductor die.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
the encapsulating comprises encapsulating the redistribution structure top side and an upper end of the conductive structure in the encapsulant; and
the method comprises exposing the upper end of the conductive structure by planarizing a top side of the encapsulant.

### Claim 20 (depends on 18)

The method of claim 18, wherein filling the first hole occurs before forming the second layer.