# US 12,183,593 B2 · Manufacturing method for manufacturing a package structure

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- Number: US 12,183,593 B2
- Document ID: US12183593B2
- Status: Granted
- Kind: B2
- Application number: 17/332,854
- Filed: 2021-05-27
- Published: 2022-12-01
- Granted: 2024-12-31
- Earliest claimed: 2021-05-27
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Chia-Pin Chen; Chia Sheng Tien; Wan-Ting Chiu; Chi Long Tsai; Cyuan-Hong Shih; Yen Liang Chen
- Web page: https://patentgrep.com/patent/US12183593B2

## CPC

- H10W 70/092: {Adapting interconnections, e.g. making engineering changes, repairing}
- H10W 70/68: Shapes or dispositions thereof
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/072: {of bump connectors}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A manufacturing method for manufacturing a package structure is provided. The manufacturing method includes: (a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface; (b) forming an under layer on the carrier to at least partially expose the flat portion; and (c) forming a dielectric layer on the under layer and covering the exposed flat portion.

## Claims

### Claim 1

A manufacturing method, comprising:
(a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface;
(b) forming an under layer on the carrier to at least partially expose the flat portion;
(b1) forming a first seed layer on the under layer;
(b2) removing a portion of the first seed layer to expose a second peripheral portion of the under layer; and
(c) forming a dielectric layer on the under layer and covering the exposed flat portion.

### Claim 2 (depends on 1)

The manufacturing method of claim 1, wherein in (c), the dielectric layer further covers a lateral side surface of the under layer.

### Claim 3 (depends on 2)

The manufacturing method of claim 2, wherein in (c), the dielectric layer contacts the flat portion.

### Claim 4 (depends on 3)

The manufacturing method of claim 3, wherein in (c), the dielectric layer contacts the first seed layer on the under layer.

### Claim 5 (depends on 1)

The manufacturing method of claim 1, wherein (b) includes: removing a first peripheral portion of the under layer to expose the flat portion.

### Claim 6 (depends on 1)

The manufacturing method of claim 1, wherein the first seed layer covers a lateral side surface of the under layer.

### Claim 7 (depends on 6)

The manufacturing method of claim 6, wherein the first seed layer contacts the flat portion.

### Claim 8 (depends on 1)

The manufacturing method of claim 1, wherein after (b1), the method further includes:
(b3) removing the portion of the first seed layer to expose a portion of the flat portion of the top surface of the carrier.

### Claim 9 (depends on 1)

The manufacturing method of claim 1, wherein (c) includes: coating a dielectric layer in a flowable state on the under layer.

### Claim 10 (depends on 9)

The manufacturing method of claim 9, wherein (c) includes: spin-coating the dielectric layer on the under layer.

### Claim 11 (depends on 1)

The manufacturing method of claim 1, wherein after (c), the method further comprises:
(d) forming a second seed layer on the dielectric layer; and
(e) removing a portion of the second seed layer.

### Claim 12 (depends on 11)

The manufacturing method of claim 11, wherein (f) (e) includes: removing the portion of the second seed layer by etching process.