# US 12,183,590 B2 · Method of performing gap filling including filling trenches between dummy gate stacks on semiconductor fins/strips with semiconductor material

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- Number: US 12,183,590 B2
- Document ID: US12183590B2
- Status: Granted
- Kind: B2
- Application number: 18/182,521
- Filed: 2023-03-13
- Published: 2023-07-06
- Granted: 2024-12-31
- Earliest claimed: 2017-09-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: De-Wei Yu; Chien-Hao Chen; Chia-Ao Chang; Pin-Ju Liang
- Web page: https://patentgrep.com/patent/US12183590B2

## CPC

- H10P 95/906: {for altering the shape of semiconductors, e.g. smoothing the surface}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/416: {of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10P 50/242: {of Group IV materials}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2924: {Structures}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3238: {being insulating materials}
- H10P 36/00: Gettering within semiconductor bodies
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

## Claims

### Claim 1

A method comprising:
forming a first dummy gate stack and a second dummy gate stack over a semiconductor region, wherein the semiconductor region is between isolation regions;
filling a trench between the first dummy gate stack and the second dummy gate stack with a semiconductor material;
replacing the first dummy gate stack and the second dummy gate stack with a first replacement gate stack and a second replacement gate stack, respectively;
after the first replacement gate stack and the second replacement gate stack are formed, removing the semiconductor material to reveal the trench again; and
forming an inter-layer dielectric filling the trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein the filling the trench comprises:
performing a first deposition process to deposit a first semiconductor layer into the trench;
etching back the first semiconductor layer; and
after the etching back, performing a second deposition process to deposit a second semiconductor layer on the first semiconductor layer.

### Claim 3 (depends on 2)

The method of claim 2 further comprising, after the first semiconductor layer is deposited and before the first semiconductor layer is etched back, performing an annealing process on the first semiconductor layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein the annealing process results in the semiconductor material in the first semiconductor layer to migrate down.

### Claim 5 (depends on 4)

The method of claim 4, wherein the migration results in a thickness of a top portion of the first semiconductor layer to be reduced by more than 25 percent.

### Claim 6 (depends on 1)

The method of claim 1, wherein the forming the semiconductor region comprises forming a semiconductor fin protruding higher than the isolation regions.

### Claim 7 (depends on 1)

The method of claim 1 further comprising:
before the trench is filled with the semiconductor material, forming a conformal dielectric layer in the trench; and
before the inter-layer dielectric is formed to fill the trench, removing the conformal dielectric layer.

### Claim 8 (depends on 1)

The method of claim 1 further comprising, before the inter-layer dielectric is formed, depositing a contact etch stop layer into the trench, wherein the inter-layer dielectric is formed over the contact etch stop layer.

### Claim 9 (depends on 1)

The method of claim 1 further comprising:
replacing a top part of the semiconductor material with a protection layer, wherein the first replacement gate stack and the second replacement gate stack are formed when the semiconductor material is protected by the protection layer; and
removing the protection layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein the filling the trench with the semiconductor material comprises depositing an amorphous semiconductor material or a poly semiconductor material.

### Claim 11 (depends on 1)

The method of claim 1, wherein the filling the trench with the semiconductor material comprises depositing silicon or silicon germanium.

### Claim 12

A method comprising:
forming a first protruding semiconductor fin and a second protruding semiconductor fin protruding higher than isolation regions;
forming a dummy gate stack on the first protruding semiconductor fin and the second protruding semiconductor fin;
forming gate spacers on sidewalls of the dummy gate stack;
growing a first epitaxy region and a second epitaxy region based on the first protruding semiconductor fin and the second protruding semiconductor fin, respectively;
forming a dielectric layer on the first epitaxy region and the second epitaxy region; and
depositing a semiconductor material on the dielectric layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the depositing the semiconductor material comprises depositing silicon.

### Claim 14 (depends on 13)

The method of claim 13, wherein the semiconductor material further comprises germanium.

### Claim 15 (depends on 12)

The method of claim 12 further comprising:
replacing the dummy gate stack with a replacement gate stack; and
removing the semiconductor material.

### Claim 16 (depends on 12)

The method of claim 12 further comprising, after the semiconductor material is deposited, performing a planarization process on the semiconductor material.

### Claim 17

A method comprising:
forming a protruding semiconductor fin protruding higher than isolation regions;
forming a first dummy gate stack and a second dummy gate stack on the protruding semiconductor fin;
forming a dielectric layer on the first dummy gate stack and the second dummy gate stack;
depositing a silicon layer filling a trench between the first dummy gate stack and the second dummy gate stack;
planarizing the silicon layer to reveal hard masks in the first dummy gate stack and the second dummy gate stack;
replacing the first dummy gate stack and the second dummy gate stack with replacement gate stacks;
after the replacement gate stacks are formed, removing the silicon layer; and
removing the dielectric layer.

### Claim 18 (depends on 17)

The method of claim 17 further comprising:
forming an epitaxy region based on the protruding semiconductor fin, wherein the dielectric layer is further formed on the epitaxy region.

### Claim 19 (depends on 18)

The method of claim 18 further comprising:
after the dielectric layer is removed, forming an inter-layer dielectric filling the trench.

### Claim 20 (depends on 19)

The method of claim 19 further comprising, before the inter-layer dielectric is formed, forming a contact etch stop layer extending into the trench.