# US 12,183,587 B2 · Method for preparing semiconductor device structure with isolation patterns having different heights > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,587 B2 - Document ID: US12183587B2 - Status: Granted - Kind: B2 - Application number: 18/584,164 - Filed: 2024-02-22 - Published: 2024-06-13 - Granted: 2024-12-31 - Earliest claimed: 2021-12-14 - Assignees: Nanya Technology Corporation - Applicants: Nanya Technology Corporation - Inventors: Ching-Cheng Chuang - Web page: https://patentgrep.com/patent/US12183587B2 ## CPC - H10P 50/73: {using masks for insulating materials} - H10P 50/283: {by chemical means} - H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for preparing a semiconductor device structure is provided. The method includes forming a target layer over a semiconductor substrate; forming an energy-sensitive layer over the target layer; performing a first energy treating process to form a plurality of first treated portions in the energy-sensitive layer; performing a second energy treating process to form a plurality of second treated portions in the energy-sensitive layer; removing the first treated portions and the second treated portions to respectively form a plurality of first openings and a plurality of second openings; transferring the first openings and the second openings into the target layer to respectively form a plurality of third openings and a plurality of fourth openings; and transferring the third openings and the fourth openings into the semiconductor substrate to respectively form a plurality of fifth openings and a plurality of sixth openings. ## Claims ### Claim 1 A method for preparing a semiconductor device structure, comprising: forming a target layer over a semiconductor substrate; forming an energy-sensitive layer over the target layer; performing a first energy treating process to form a plurality of first treated portions in the energy-sensitive layer; performing a second energy treating process to form a plurality of second treated portions in the energy-sensitive layer; removing the first treated portions and the second treated portions to respectively form a plurality of first openings and a plurality of second openings; transferring the first openings and the second openings into the target layer to respectively form a plurality of third openings and a plurality of fourth openings; transferring the third openings and the fourth openings into the semiconductor substrate to respectively form a plurality of fifth openings and a plurality of sixth openings; filling the fifth openings and the sixth openings with an isolation structure; and removing the target layer after the fifth openings and the sixth openings are formed in the semiconductor substrate; wherein the isolation structure has different heights in different cross-sections; wherein the first treated portions and the second treated portions extend along from different directions; wherein the first treated portions are parallel to each other, and wherein each of the second treated portions is located between and in direct contact with any two adjacent ones of the first treated portions. ### Claim 2 (depends on 1) The method for preparing a semiconductor device structure of claim 1, wherein the first energy treating process and the second energy treating process are electron-beam (e-beam) writing processes. ### Claim 3 (depends on 1) The method for preparing a semiconductor device structure of claim 1, wherein the first treated portions are formed by applying a first energy to the energy-sensitive layer, and the second treated portions are formed by applying a second energy to the energy-sensitive layer, and wherein the second energy is greater than the first energy. ### Claim 4 (depends on 3) The method for preparing a semiconductor device structure of claim 3, wherein the first treated portions have a first height, and the second treated portions have a second height, and wherein the second height is greater than the first height. ### Claim 5 (depends on 1) The method for preparing a semiconductor device structure of claim 1, further comprising: removing the energy-sensitive layer after the third openings and the fourth openings are formed in the target layer. ### Claim 6 (depends on 1) The method for preparing a semiconductor device structure of claim 1, wherein the target layer is removed before the isolation structure is formed. ### Claim 7 (depends on 1) The method for preparing a semiconductor device structure of claim 1, wherein the energy-sensitive layer includes a cross-linking compound having a cross-linking functional group. ### Claim 8 (depends on 7) The method for preparing a semiconductor device structure of claim 7, wherein the cross-linking functional group includes a double bond. ### Claim 9 (depends on 1) The method for preparing a semiconductor device structure of claim 1, wherein bottom surfaces of the first treated portions are higher than bottom surfaces of the second treated portions. ### Claim 10 (depends on 1) The method for preparing a semiconductor device structure of claim 1, wherein bottom surfaces of the first openings in the energy-sensitive layer are higher than bottom surfaces of the second openings in the energy-sensitive layer. ### Claim 11 (depends on 1) The method for preparing a semiconductor device structure of claim 1, wherein bottom surfaces of the third openings in the target layer are higher than bottom surfaces of the fourth openings in the target layer. ### Claim 12 (depends on 1) The method for preparing a semiconductor device structure of claim 1, wherein bottom surfaces of the fifth openings in the semiconductor substrate are higher than bottom surfaces of the sixth openings in the semiconductor substrate.