# US 12,183,585 B2 · Manufacturing method of semiconductor structure including complementary first and second mask patterns

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- Number: US 12,183,585 B2
- Document ID: US12183585B2
- Status: Granted
- Kind: B2
- Application number: 17/476,772
- Filed: 2021-09-16
- Published: 2022-03-24
- Granted: 2024-12-31
- Earliest claimed: 2020-09-18
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Kui Zhang; Zhan Ying
- Web page: https://patentgrep.com/patent/US12183585B2

## CPC

- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/01: {Manufacture or treatment}
- H10P 76/202: {for lift-off processes}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a manufacturing method of a semiconductor structure, including: providing a substrate; forming a first mask layer having a first mask pattern on the substrate, and etching the substrate by using the first mask layer as a mask to form active regions; forming several discrete bitlines on the active regions; forming a sacrificial layer between adjacent bitlines; forming a second mask layer having a second mask pattern on the sacrificial layer, the first mask pattern and the second mask pattern being complementary to each other; and etching the sacrificial layer by using the second mask layer and the bitlines as masks to form a plurality of contact structures. The embodiment of the present disclosure is beneficial to reducing the manufacturing cost of the semiconductor structure.

## Claims

### Claim 1

A manufacturing method of a semiconductor structure, comprising:
providing a substrate;
forming a first mask layer having a first mask pattern on the substrate, and etching the substrate by using the first mask layer as a mask to form active regions;
forming a plurality of discrete bitlines on the active regions;
forming a sacrificial layer between adjacent bitlines;
forming a second mask layer having a second mask pattern on the sacrificial layer, the first mask pattern and the second mask pattern being complementary to each other; and
etching the sacrificial layer by using the second mask layer and the bitlines as masks to form a plurality of contact hole structures.

### Claim 2 (depends on 1)

The manufacturing method of a semiconductor structure according to claim 1, wherein a first photomask for forming the first mask pattern and a second photomask for forming the second mask pattern are the same.

### Claim 3 (depends on 2)

The manufacturing method of a semiconductor structure according to claim 2, wherein the first mask pattern comprises elongated patterns, and the second mask pattern comprises elongated openings.

### Claim 4 (depends on 3)

The manufacturing method of a semiconductor structure according to claim 3, wherein the elongated patterns and the elongated openings are arranged in an array.

### Claim 5 (depends on 4)

The manufacturing method of a semiconductor structure according to claim 4, wherein the elongated pattern and the elongated opening are the same in size and shape.

### Claim 6 (depends on 4)

The manufacturing method of a semiconductor structure according to claim 4, wherein projections of the elongated pattern and the elongated opening on the substrate are coincided.

### Claim 7 (depends on 1)

The manufacturing method of a semiconductor structure according to claim 1, wherein the bitline comprises a cap layer, the cap layer is located on top of the bitline, and the cap layer and the sacrificial layer have etch selectivity.

### Claim 8 (depends on 2)

The manufacturing method of a semiconductor structure according to claim 2, wherein the first mask pattern is formed by using the first photomask and the second photomask; the second mask pattern is formed by using the first photomask and the second photomask.

### Claim 9 (depends on 8)

The manufacturing method of a semiconductor structure according to claim 8, wherein the forming the first mask pattern by using the first photomask and the second photomask comprises:
forming an unpatterned first mask layer on the substrate;
forming a first photoresist line extending in a first direction on the first mask layer by using the first photomask;
etching the first mask layer by using the first photoresist line to form a first mask line;
forming a second photoresist line extending in a second direction on the first mask line by using the second photomask; and
etching the first mask line by using the second photoresist line to form an elongated pattern.

### Claim 10 (depends on 9)

The manufacturing method of a semiconductor structure according to claim 9, wherein the forming the second mask pattern by using the first photomask and the second photomask comprises:
forming an unpatterned second mask layer on the sacrificial layer;
forming a third mask layer on the second mask layer;
forming a first photoresist opening extending in the first direction on the third mask layer by using the first photomask;
etching the third mask layer by using the first photoresist opening to form a first mask opening;
forming a second photoresist opening extending in the second direction on the first mask opening by using the second photomask; and
etching the second mask layer by using the second photoresist opening and the first mask opening to form an elongated opening.

### Claim 11 (depends on 10)

The manufacturing method of a semiconductor structure according to claim 10, wherein the nature of a photoresist forming the first photoresist line and the nature of a photoresist forming the first photoresist opening are different; the nature of a photoresist forming the second photoresist line and the nature of a photoresist forming the second photoresist opening are different are different.

### Claim 12 (depends on 9)

The manufacturing method of a semiconductor structure according to claim 9, further comprising: forming a repair layer on sidewalls of the elongated pattern.

### Claim 13 (depends on 2)

The manufacturing method of a semiconductor structure according to claim 2, wherein a projection of the second mask pattern on the substrate completely covers a projection of the first mask pattern on the substrate.

### Claim 14 (depends on 2)

The manufacturing method of a semiconductor structure according to claim 2, wherein an inclined angle between an extension direction of the second mask pattern and an extension direction of the first mask pattern is less than 30 degrees.

### Claim 15 (depends on 2)

The manufacturing method of a semiconductor structure according to claim 2, wherein the first mask pattern and the second mask pattern can be formed by one or a combination of a Self-aligned Double Patterning process and a Reverse Self-aligned Double Patterning process.