# US 12,183,576 B2 · Preparation method for semiconductor structure

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- Number: US 12,183,576 B2
- Document ID: US12183576B2
- Status: Granted
- Kind: B2
- Application number: 17/968,981
- Filed: 2022-10-19
- Published: 2023-02-09
- Granted: 2024-12-31
- Earliest claimed: 2020-08-24
- Assignees: Enkris Semiconductor, Inc.
- Applicants: Enkris Semiconductor, Inc.
- Inventors: Peng Xiang; Kai Cheng
- Web page: https://patentgrep.com/patent/US12183576B2

## CPC

- H10P 14/3822: {Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing}
- C30B 25/04: Pattern deposit, e.g. by using masks
- C30B 25/183: {being provided with a buffer layer, e.g. a lattice matching layer}
- C30B 25/186: {being specially pre-treated by, e.g. chemical or physical means}
- C30B 29/406: {Gallium nitride}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2904: {Silicon carbide}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2908: {Nitrides}
- H10P 14/2921: {being crystalline insulating materials}
- H10P 14/3216: {Nitrides}
- H10P 14/3248: {consisting of two layers}
- H10P 14/3251: {consisting of three or more layers}
- H10P 14/3416: {Nitrides}
- H10P 14/3442: {N-type}
- H10P 14/3441: {Conductivity type}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C30B: SINGLE-CRYSTAL GROWTH (by using ultra-high pressure, e.g. for the formation of diamonds, B01J3/06); UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL (zone-refining of metals or alloys C22B); PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (casting of metals, casting of other substances by the same processes or devices B22D; working of plastics B29; modifying the physical structure of metals or alloys C21D, C22F); SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (for producing semiconductor devices or parts thereof H10); APPARATUS THEREFOR

## Abstract

Disclosed is a preparation method for a semiconductor structure. The semiconductor structure includes: a substrate; an epitaxial layer and an epitaxial structure that are stacked on the substrate in sequence. The epitaxial layer is doped with a doping element. In the forming process, a sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that a concentration of the doping element in the epitaxial layer is lower than a preset value. In this application, the sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that the concentration of the doping element in the epitaxial layer is lower than the preset value, so as to prevent the doping element in the epitaxial layer from being precipitated upward into an upper-layer structure, ensure the mobility of electrons in a channel layer, and improve the performance of a device.

## Claims

### Claim 1

A preparation method for a semiconductor structure, comprising:
S1: forming a first epitaxial structure on a substrate, wherein the first epitaxial structure is doped with a doping element;
S2: forming a sacrificial layer on the first epitaxial structure;
S3: etching the sacrificial layer; and
S4: continuing to grow a second epitaxial structure on the first epitaxial structure on which the sacrificial layer has been etched, wherein
before step S4, steps S2 and S3 are repeated multiple times until the concentration of the doping element in the first epitaxial structure is lower than a preset value, wherein a material of the sacrificial layer comprises a combination of one or more of InN, InGaN, InAlN, InAlGaN, and GaN.

### Claim 2 (depends on 1)

The preparation method for a semiconductor structure of claim 1, wherein the first epitaxial structure is a buffer layer, the doping element is in the buffer layer; and the second epitaxial structure comprises at least a channel layer and a barrier layer that are stacked in sequence.

### Claim 3 (depends on 1)

The preparation method for a semiconductor structure of claim 1, wherein the first epitaxial structure comprises a buffer layer, a first N-type semiconductor layer, a second N-type semiconductor layer, and a P-type semiconductor layer that are stacked in sequence, the doping element is in the P-type semiconductor layer; and the second epitaxial structure comprises at least a third N-type semiconductor layer.

### Claim 4 (depends on 3)

The preparation method for a semiconductor structure of claim 3, wherein the first N-type semiconductor layer is an N-type doped GaN layer; the second N-type semiconductor layer is an N-type lightly doped GaN layer; and the third N-type semiconductor layer is an N-type heavily doped GaN layer.

### Claim 5 (depends on 1)

The preparation method for a semiconductor structure of claim 1, wherein the first epitaxial structure comprises at least a buffer layer and a first P-type semiconductor layer that are stacked in sequence, the doping element is in the P-type semiconductor layer; and the second epitaxial structure comprises at least an N-type semiconductor layer and a second P-type semiconductor layer that are stacked in sequence.

### Claim 6 (depends on 5)

The preparation method for a semiconductor structure of claim 5, wherein the first P-type semiconductor layer is a P-type GaN layer; the N-type semiconductor layer is an N-type GaN layer; and the second P-type semiconductor layer is a P-type GaN layer.

### Claim 7 (depends on 1)

The preparation method for a semiconductor structure of claim 1, wherein a thickness of the sacrificial layer ranges from 1 nm to 1 μm.

### Claim 8 (depends on 1)

The preparation method for a semiconductor structure of claim 1, further comprising:
growing a protective layer between the first epitaxial structure and the sacrificial layer.

### Claim 9 (depends on 8)

The preparation method for a semiconductor structure of claim 8, wherein a material of the protective layer comprises a combination of one or more of AIN, AlInGaN, and AlGaN.

### Claim 10 (depends on 1)

The preparation method for a semiconductor structure of claim 1, wherein the doping element in the first epitaxial structure is iron or magnesium; and the concentration of the doping element is constant or varies with the thickness.

### Claim 11 (depends on 1)

The preparation method for a semiconductor structure of claim 1, wherein the preset value is below an order of 2×1018 atoms/cm3.

### Claim 12 (depends on 1)

The preparation method for a semiconductor structure of claim 1, wherein steps S1, S2, S3, and S4 are sequentially completed in a same reaction chamber.

### Claim 13 (depends on 1)

The preparation method for a semiconductor structure of claim 1, wherein in step S3, the temperature in the reaction chamber is higher than 400 degrees Celsius, and the sacrificial layer is etched using a gas.

### Claim 14 (depends on 13)

The preparation method for a semiconductor structure of claim 13, wherein the gas is one or a combination of more of hydrogen, ammonia, hydrogen chloride, and chlorine.

### Claim 15 (depends on 1)

The preparation method for a semiconductor structure of claim 1, wherein in step S3, the sacrificial layer is completely or partially etched.

### Claim 16 (depends on 1)

The preparation method for a semiconductor structure of claim 1, wherein the substrate is Si, SiC, GaN, AlN, or sapphire.