# US 12,183,429 B2 · Turbo mode SRAM for high performance

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- Number: US 12,183,429 B2
- Document ID: US12183429B2
- Status: Granted
- Kind: B2
- Application number: 17/848,599
- Filed: 2022-06-24
- Published: 2022-10-13
- Granted: 2024-12-31
- Earliest claimed: 2017-09-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Michael Clinton
- Web page: https://patentgrep.com/patent/US12183429B2

## CPC

- G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits}
- G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)}
- G11C 7/08: Control thereof
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 11/419: Read-write [R-W] circuits
- H10B 10/00: Static random access memory [SRAM] devices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

## Claims

### Claim 1

A system comprising:
a sense amplifier circuit coupled between a bit line pair and configured to sense a voltage differential between the bit line pair;
a sense amplifier control circuit configured to send a sense amplifier enable signal to the sense amplifier circuit at a predetermined frequency rate based on a voltage of a tracking bit line (DBL);
a turbo circuit configured to modify the voltage of the DBL enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate, wherein the turbo circuit is configured to control the voltage of the DBL based upon a turbo signal and a voltage of a tracking word line (DWL);
a turbo enabling circuit configured to generate the turbo signal and including a NAND circuit; and
a tracking cell coupled between the DWL and the DBL, wherein:
the turbo circuit is coupled between the DWL and the DBL;
the tracking cell includes cross-coupled inverters; and
an output of one of the cross-coupled inverters is tied to a supply voltage.

### Claim 2 (depends on 1)

The system of claim 1, wherein:
the tracking cell is configured to track or imitate read or write operations at different locations within an array of a memory device;
the sense amplifier enable signal is generated when the voltage of the DBL falls below a threshold voltage; and
the turbo signal decreases the voltage of the DBL voltage.

### Claim 3 (depends on 1)

The system of claim 1, wherein the tracking cell is configured to pull-down the voltage of the DBL.

### Claim 4 (depends on 1)

The system of claim 1, further comprising:
a voltage detector circuit configured to detect a voltage difference between a supply voltage and a reference voltage; and
a dual inverter circuit coupled to the voltage detector circuit configured to generate the turbo signal based on the voltage difference.

### Claim 5 (depends on 4)

The system of claim 4, further comprising:
an inverter circuit electrically coupled to the dual inverter circuit and configured to generate a handshake signal; and
a logic gate configured to provide the turbo signal to a clock generator based upon the handshake signal.

### Claim 6 (depends on 1)

The system device of claim 1, further comprising:
a voltage detector circuit configured to detect a voltage difference between a supply voltage and a reference voltage, wherein
the NAND circuit is coupled to the voltage detector circuit and a turbo enable input signal; and
an inverter circuit coupled to an output of the NAND circuit, the inverter circuit being configured to generate the turbo signal based on the voltage difference and the turbo enable input signal.

### Claim 7 (depends on 1)

The system of claim 1, further comprising a timer transistor gated by the voltage of the tracking word line and the timer transistor is coupled to the turbo circuit.

### Claim 8 (depends on 1)

The system of claim 1, wherein the turbo circuit includes a transistor having a gate terminal configured to receive the turbo signal and a source/drain terminal coupled to the DBL.

### Claim 9 (depends on 1)

The system of claim 1, wherein the turbo circuit includes a logic gate having a first input terminal configured to receive the turbo signal and a second input terminal coupled to the DBL.

### Claim 10

A method comprising:
generating a sense amplifier enable signal based on a voltage of a tracking bit line (DBL);
injecting a turbo signal into a turbo circuit;
modifying the voltage of the DBL based on the turbo signal and a voltage of a tracking word line (DWL), wherein:
a tracking cell is coupled between the DWL and the DBL and includes cross-coupled inverters;
an output of one of the cross-coupled inverters is coupled to a supply voltage; and
the turbo circuit is coupled between the DWL and the DBL; and
generating the turbo signal, using a NAND circuit, based on a turbo enable input signal.

### Claim 11 (depends on 10)

The method of claim 10, wherein injecting the turbo signal into the turbo circuit decreases the voltage of the DBL and the decreased voltage of the DBL triggers the sense enable signal to enable performance of read or write operations of a memory device.

### Claim 12 (depends on 10)

The method of claim 10, wherein the turbo circuit modifies the voltage of the DBL by pulling down the voltage of the DBL using at least two transistors coupled together in series.

### Claim 13 (depends on 10)

The method of claim 10, wherein the turbo circuit modifies the voltage of the DBL when the voltage of the DWL and the turbo signal are a logic high.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
detecting, using a voltage detector circuit, a voltage difference between a supply voltage and a reference voltage; and
generating, using a dual inverter circuit coupled to the voltage detector circuit, the turbo signal when the supply voltage exceeds the reference voltage.

### Claim 15 (depends on 10)

The method of claim 10, further comprising:
detecting, using a voltage detector circuit, a voltage difference between a supply voltage and a reference voltage; and
generating the turbo signal, using the NAND circuit, based on the supply voltage exceeding the reference voltage and the turbo enable input signal.

### Claim 16 (depends on 10)

The method of claim 10, further comprising a timer transistor gated by the voltage of the tracking word line and the timer transistor is coupled to the turbo circuit.

### Claim 17

A memory device comprising:
a tracking word line (DWL);
a tracking bit line (DBL);
an inverter circuit configured to generate a sense amplifier enable signal based on a voltage of the DBL;
a turbo enabling circuit configured to generate a turbo signal and including a NAND circuit;
a turbo circuit coupled between the DWL and the DBL and configured to control the voltage of the DBL based on the turbo signal and a voltage of the DWL; and
a tracking cell coupled between the DWL and the DBL and includes cross-coupled inverters, wherein an output of one of the cross-coupled inverters is coupled to a supply voltage.

### Claim 18 (depends on 17)

The memory device of claim 17, wherein the turbo circuit comprises:
a first transistor having a gate terminal coupled to the turbo signal and a source/drain terminal coupled to the DBL; and
a second transistor having a gate terminal coupled to the DWL and a source/drain terminal coupled to another source/drain terminal of the first transistor.

### Claim 19 (depends on 17)

The memory device of claim 17, wherein the turbo signal is generated based on an applied voltage to the inverter circuit exceeding a predetermined reference voltage.

### Claim 20 (depends on 17)

The memory device of claim 17, further comprising a timer transistor gated by the voltage of the tracking word line and the timer transistor is coupled to the turbo circuit.