# US 12,183,427 B1 · System and method for write clock double data rate duty cycle correction

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- Number: US 12,183,427 B1
- Document ID: US12183427B1
- Status: Granted
- Kind: B1
- Application number: 17/967,040
- Filed: 2022-10-17
- Granted: 2024-12-31
- Earliest claimed: 2022-10-17
- Assignees: Cadence Design Systems, Inc.
- Applicants: Cadence Design Systems, Inc.
- Inventors: Sachin Ramesh Gugwad; Hari Anand Ravi
- Web page: https://patentgrep.com/patent/US12183427B1

## CPC

- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 7/1066: {Output synchronization}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 2207/2227: Standby or low power modes
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure relates to a system and method for duty cycle correction is provided. The method may include receiving a signal at a duty cycle adjuster and performing serializer clock duty cycle correction at the duty cycle adjuster. The method may further include performing true clock duty cycle correction at a transmitter duty cycle adjuster and performing complementary duty cycle distortion correction at the transmitter duty cycle adjuster.

## Claims

### Claim 1

A duty cycle correction method, comprising:
receiving a signal at a duty cycle adjuster;
performing serializer clock duty cycle correction at the duty cycle adjuster;
performing true clock duty cycle correction at a transmitter duty cycle adjuster, wherein the transmitter duty cycle adjuster is included within a write clock (WCK) transmit path; and
performing complementary duty cycle distortion correction at the transmitter duty cycle adjuster.

### Claim 2 (depends on 1)

The duty cycle correction method of claim 1, further comprising:
receiving an output of the transmitter duty cycle adjuster at a duty cycle monitor.

### Claim 3 (depends on 1)

The duty cycle correction method of claim 1, further comprising:
providing a true clock duty cycle correction output to a dynamic random access memory.

### Claim 4 (depends on 1)

The duty cycle correction method of claim 1, further comprising:
providing a complementary clock duty cycle correction output to a dynamic random access memory.

### Claim 5 (depends on 1)

The duty cycle correction method of claim 1, further comprising:
training an optimal reference voltage prior to performing transmit clock duty cycle correction.

### Claim 6 (depends on 2)

The duty cycle correction method of claim 2, further comprising:
determining one or more final duty cycle correction bits of the true clock duty cycle correction of the transmitter based upon, at least in part, an output from the duty cycle monitor.

### Claim 7 (depends on 2)

The duty cycle correction method of claim 2, further comprising:
determining one or more final duty cycle correction bits of the complementary clock duty cycle correction of the transmitter based upon, at least in part, an output from the duty cycle monitor.

### Claim 8 (depends on 1)

The duty cycle correction method of claim 1, further comprising:
receiving an output from the write clock (WCK) transmit path at a receiver.

### Claim 9 (depends on 8)

The duty cycle correction method of claim 8, further comprising:
receiving an output from the receiver at a duty cycle monitor.

### Claim 10

A duty cycle correction system, comprising:
a duty cycle adjuster configured to receive a signal and to perform serializer clock duty cycle correction; and
a transmitter duty cycle adjuster configured to perform true clock duty cycle correction, wherein the transmitter duty cycle adjuster is further configured to perform complementary duty cycle distortion correction, wherein the transmitter duty cycle adjuster is included within a write clock (WCK) transmit path.

### Claim 11 (depends on 10)

The duty cycle correction system of claim 10, further comprising:
a duty cycle monitor configured to receive an output of the transmitter duty cycle adjuster.

### Claim 12 (depends on 10)

The duty cycle correction system of claim 10, further comprising:
a dynamic random access memory configured to receive a true clock duty cycle correction output.

### Claim 13 (depends on 10)

The duty cycle correction system of claim 10, further comprising:
a dynamic random access memory configured to receive a complementary clock duty cycle correction output.

### Claim 14 (depends on 10)

The duty cycle correction system of claim 10, wherein an optimal reference voltage is trained prior to performing transmit clock duty cycle correction.

### Claim 15 (depends on 11)

The duty cycle correction system of claim 11, further comprising:
determining one or more final duty cycle correction bits of the true clock duty cycle correction of the transmitter based upon, at least in part, an output from the duty cycle monitor.

### Claim 16 (depends on 11)

The duty cycle correction system of claim 11, further comprising:
determining one or more final duty cycle correction bits of the complementary clock duty cycle correction of the transmitter based upon, at least in part, an output from the duty cycle monitor.

### Claim 17 (depends on 10)

The duty cycle correction system of claim 10, further comprising:
a receiver configured to receive an output from the write clock (WCK) transmit path.

### Claim 18 (depends on 17)

The duty cycle correction system of claim 17, further comprising:
a duty cycle monitor configured to receive an output from the receiver.