# US 12,183,425 B2 · Data reading/writing method, memory, storage apparatus, and terminal

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- Number: US 12,183,425 B2
- Document ID: US12183425B2
- Status: Granted
- Kind: B2
- Application number: 17/893,067
- Filed: 2022-08-22
- Published: 2022-12-22
- Granted: 2024-12-31
- Earliest claimed: 2020-02-21
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: Huifang Jiao; Ran He; Luming Fan; Yue Pan
- Web page: https://patentgrep.com/patent/US12183425B2

## CPC

- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 11/4094: Bit-line management or control circuits
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/067: {Single-ended amplifiers}
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C 11/418: Address circuits
- G11C 11/419: Read-write [R-W] circuits
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 7/02: with means for avoiding parasitic signals
- G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory includes S storage blocks, N global bitlines, and a signal amplification circuit. Each of the S storage blocks is connected to the N global bitlines, the N global bitlines are connected to the signal amplification circuit, the signal amplification circuit is configured to amplify electrical signals on the N global bitlines, and each storage block includes N columns of storage units, N local bitlines, and N bitline switches. In each storage block, storage units in an ith column are connected to an ith local bitline, the ith local bitline is connected to an ith global bitline by using an ith bitline switch in the N bitline switches. A memory array is fine-grained, so that ith local bitlines in the S storage blocks can share one global bitline.

## Claims

### Claim 1

A memory, comprising:
S storage blocks;
N global bitlines;
a signal amplification circuit, wherein:
each of the S storage blocks is connected to the N global bitlines,
the N global bitlines are connected to the signal amplification circuit,
the signal amplification circuit is configured to amplify electrical signals on the N global bitlines,
S and N are positive integers and S≥2,
each storage block comprises N columns of storage units, N local bitlines, and
N bitline switches; and
in each storage block:
storage units in an ith column in the N columns of storage units are connected to an ith local bitline in the N local bitlines,
an ith bitline switch of the N bitline switches,
the ith local bitline is connected to an ith global bitline in the N global bitlines via the ith bitline switch in the N bitline switches, N is a positive integer, and i is a positive integer not greater than N; and
wherein:
each storage block is divided into T storage sub-blocks, the storage sub-blocks in the memory are arranged in S rows×T columns, each column of storage sub-blocks forms one storage domain, the memory comprises T storage domains, the memory further comprises W global wordlines, T and W are positive integers, T≥2, and each of the T storage domains comprises W rows of storage units, W local wordlines, and W wordline switches; and
in each storage domain, storage units in a vth row in the W rows of storage units are connected to a vth local wordline in the W local wordlines, the vth local wordline is connected to a vth global wordline in the W global wordlines by using a vth wordline switch in the W wordline switches, W is a positive integer, and v is a positive integer not greater than W.

### Claim 2 (depends on 1)

The memory according to claim 1, wherein the signal amplification circuit comprises N differential amplifiers, and an ith differential amplifier in the N differential amplifiers is configured to amplify an electrical signal on the ith global bitline.

### Claim 3 (depends on 1)

The memory according to claim 1, wherein the signal amplification circuit comprises P multiplexers and P differential amplifiers, an input end of a kth multiplexer in the P multiplexers is connected to at least two of the N global bitlines, an output end of the kth multiplexer in the P multiplexers is connected to a kth differential amplifier in the P differential amplifiers, the kth multiplexer in the P multiplexers is configured to select, for outputting, one electrical signal from electrical signals transmitted on the at least two global bitlines, P is a positive integer not greater than N, and k is a positive integer not greater than P.

### Claim 4 (depends on 1)

The memory according to claim 1, wherein each storage block further comprises N first control lines separately connected to control inputs of the N bitline switches, the N first control lines are all connected to a first control circuit, and the first control circuit is configured to control the N bitline switches to be turned on or off.

### Claim 5 (depends on 1)

The memory according to claim 1, wherein the memory further comprises a bitline drive circuit, and the bitline drive circuit is connected to the N global bitlines, and is configured to input electrical signals to the N global bitlines.

### Claim 6 (depends on 1)

The memory according to claim 1, wherein the storage units in each storage block are arranged in M rows×N columns, each storage block further comprises M wordlines, storage units in a jth row in the M rows×N columns of storage units are connected to a jth wordline in the M wordlines, M is a positive integer, and j is a positive integer not greater than M.

### Claim 7 (depends on 6)

The memory according to claim 6, wherein the memory further comprises a wordline drive circuit, and the wordline drive circuit is connected to wordlines in the S storage blocks, and is configured to control a potential of the wordline.

### Claim 8 (depends on 1)

The memory according to claim 1, wherein each storage domain further comprises W second control lines separately connected to the W wordline switches, the W second control lines are all connected to a second control circuit, and the second control circuit is configured to control the W wordline switches to be turned on or off.

### Claim 9 (depends on 1)

The memory according to claim 1, wherein the memory further comprises a wordline drive circuit, and the wordline drive circuit is connected to global wordlines in the T storage domains, and is configured to control a potential of the global wordline.

### Claim 10

A storage apparatus, comprising:
a memory;
a storage controller coupled to the memory;
the memory comprises:
S storage blocks,
N global bitlines, and
a signal amplification circuit,
each of the S storage blocks is connected to the N global bitlines,
the N global bitlines are connected to the signal amplification circuit,
the signal amplification circuit is configured to amplify electrical signals on the N global bitlines,
S and N are positive integers, and S≥2,
each storage block comprises N columns of storage units,
N local bitlines,
N bitline switches coupled to the N local bitlines and N global bitlines; and
in each storage block,
storage units in an ith column in the N columns of storage units are connected to an ith local bitline in the N local bitlines, the ith local bitline is connected to an ith global bitline in the N global bitlines via an ith bitline switch in the N bitline switches, N is a positive integer, and i is a positive integer not greater than N; and
wherein:
each storage block is divided into T storage sub-blocks, the storage sub-blocks in the memory are arranged in S rows×T columns, each column of storage sub-blocks forms one storage domain, the memory comprises T storage domains, the memory further comprises W global wordlines, T and W are positive integers, T≥2, and each of the T storage domains comprises W rows of storage units, W local wordlines, and W wordline switches; and
in each storage domain, storage units in a vth row in the W rows of storage units are connected to a vth local wordline in the W local wordlines, the vth local wordline is connected to a vth global wordline in the W global wordlines by using a vth wordline switch in the W wordline switches, W is a positive integer, and v is a positive integer not greater than W.

### Claim 11 (depends on 10)

The memory according to claim 10, wherein the signal amplification circuit comprises N differential amplifiers, and an ith differential amplifier in the N differential amplifiers is configured to amplify an electrical signal on the ith global bitline.

### Claim 12 (depends on 10)

The memory according to claim 10, wherein the signal amplification circuit comprises P multiplexers and P differential amplifiers, an input end of a kth multiplexer in the P multiplexers is connected to at least two of the N global bitlines, an output end of the kth multiplexer in the P multiplexers is connected to a kth differential amplifier in the P differential amplifiers, the kth multiplexer in the P multiplexers is configured to select, for outputting, one electrical signal from electrical signals transmitted on the at least two global bitlines, P is a positive integer not greater than N, and k is a positive integer not greater than P.

### Claim 13 (depends on 10)

The memory according to claim 10, wherein each storage block further comprises N first control lines separately connected to control inputs of the N bitline switches, the N first control lines are all connected to a first control circuit, and the first control circuit is configured to control the N bitline switches to be turned on or off.

### Claim 14 (depends on 10)

The memory according to claim 10, wherein the memory further comprises a bitline drive circuit, and the bitline drive circuit is connected to the N global bitlines, and is configured to input electrical signals to the N global bitlines.

### Claim 15

A terminal, comprising a processor, a storage controller and a memory, wherein the memory is coupled to the processor, wherein the memory comprises S storage blocks, N global bitlines, and a signal amplification circuit, wherein each of the S storage blocks is connected to the N global bitlines, the N global bitlines are connected to the signal amplification circuit, the signal amplification circuit is configured to amplify electrical signals on the N global bitlines, S and N are positive integers, S≥2, and each storage block comprises N columns of storage units, N local bitlines, and N bitline switches; and
in each storage block, storage units in an ith column in the N columns of storage units are connected to an ith local bitline in the N local bitlines, the ith local bitline is connected to an ith global bitline in the N global bitlines by using an ith bitline switch in the N bitline switches, N is a positive integer, and i is a positive integer not greater than N; and
wherein:
each storage block is divided into T storage sub-blocks, the storage sub-blocks in the memory are arranged in S rows×T columns, each column of storage sub-blocks forms one storage domain, the memory comprises T storage domains, the memory further comprises W global wordlines, T and W are positive integers, T≥2, and each of the T storage domains comprises W rows of storage units, W local wordlines, and W wordline switches; and
in each storage domain, storage units in a vth row in the W rows of storage units are connected to a vth local wordline in the W local wordlines, the vth local wordline is connected to a vth global wordline in the W global wordlines by using a vth wordline switch in the W wordline switches, W is a positive integer, and v is a positive integer not greater than W.

### Claim 16 (depends on 15)

The memory according to claim 15, wherein the signal amplification circuit comprises N differential amplifiers, and an ith differential amplifier in the N differential amplifiers is configured to amplify an electrical signal on the ith global bitline.

### Claim 17 (depends on 15)

The memory according to claim 15, wherein the signal amplification circuit comprises P multiplexers and P differential amplifiers, an input end of a kth multiplexer in the P multiplexers is connected to at least two of the N global bitlines, an output end of the kth multiplexer in the P multiplexers is connected to a kth differential amplifier in the P differential amplifiers, the kth multiplexer in the P multiplexers is configured to select, for outputting, one electrical signal from electrical signals transmitted on the at least two global bitlines, P is a positive integer not greater than N, and k is a positive integer not greater than P.

### Claim 18 (depends on 15)

The memory according to claim 15, wherein each storage block further comprises N first control lines separately connected to control ends of the N bitline switches, the N first control lines are all connected to a first control circuit, and the first control circuit is configured to control the N bitline switches to be turned on or off.

### Claim 19 (depends on 15)

The memory according to claim 15, wherein the memory further comprises a bitline drive circuit, and the bitline drive circuit is connected to the N global bitlines, and is configured to input electrical signals to the N global bitlines.