# US 12,183,424 B2 · Bit-cell architecture based in-memory compute > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,424 B2 - Document ID: US12183424B2 - Status: Granted - Kind: B2 - Application number: 17/954,060 - Filed: 2022-09-27 - Published: 2023-03-30 - Granted: 2024-12-31 - Earliest claimed: 2021-09-30 - Assignees: STMicroelectronics International N.V. - Applicants: STMicroelectronics International N.V. - Inventors: Harsh Rawat; Kedar Janardan Dhori; Promod Kumar; Nitin Chawla; Manuj Ayodhyawasi - Web page: https://patentgrep.com/patent/US12183424B2 ## CPC - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/1087: {Data input latches} - G06N 3/063: using electronic means - G11C 7/1069: {I/O lines read out arrangements} - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - G11C 11/412: using field-effect transistors only - G11C 11/54: using elements simulating biological cells, e.g. neuron - G11C: STATIC STORES (semiconductor memory devices H10B) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell. ## Claims ### Claim 1 An in-memory-compute memory cell, comprising: a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell, wherein the first bit-cell comprises a read-word line, and the second bit-cell comprises a read-word line, and, in an in-memory-compute mode of operation, the in-memory-compute cell XORs data stored in the latches with data provided on the read-word lines. ### Claim 2 (depends on 1) The in-memory-compute cell of claim 1, wherein the first bit-cell and the second bit-cell are foundry bit-cells. ### Claim 3 (depends on 2) The in-memory-compute cell of claim 2, wherein the first bit-cell and second bit-cell are eight transistor bit-cells. ### Claim 4 (depends on 1) The in-memory-compute cell of claim 1, wherein the first bit-cell comprises a read-bit line, and the second bit-cell comprises a read-bit line, and, in the in-memory-compute mode of operation, the in-memory-compute cell XORs feature data stored in the latches with weight data provided on the read-word lines. ### Claim 5 A memory array, comprising: a plurality of bit-cells of the memory array arranged as a set of rows of bit-cells of the memory array intersecting a plurality of columns of the memory array; and a plurality of in-memory-compute (IMC) cells of the memory array arranged as a set of rows of IMC cells of the memory array intersecting the plurality of columns of the memory array, wherein each of the IMC cells of the memory array includes: a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell, wherein, the first bit-cells of the IMC cells comprise a read-word line, and the second bit-cells of the IMC cells comprise a read-word line, and, in an in-memory-compute mode of operation of the array, the IMC cells selectively XOR data stored in the latches with data provided on the read-word lines. ### Claim 6 (depends on 5) The memory array of claim 5, wherein the plurality of bit-cells, the first bit-cells of the IMC cells, and the second bit-cells of the IMC cells are foundry bit-cells. ### Claim 7 (depends on 6) The memory array of claim 6, wherein, the plurality of bit-cells are six transistor bit-cells; and the first bit-cells of the IMC cells and the second bit-cells of the IMC cells are eight transistor bit-cells. ### Claim 8 (depends on 5) The memory array of claim 5, wherein the first bit-cells of the IMC cells comprise a read-bit line, and the second bit-cells of the IMC cells comprise a read-bit line, and, in the in-memory-compute mode of operation of the array, the IMC cells selectively XOR feature data stored in the latches with weight data provided on the read-word lines. ### Claim 9 (depends on 5) The memory array of claim 5, wherein the array comprises pre-charging circuitry coupled to the plurality of IMC cells. ### Claim 10 (depends on 9) The memory array of claim 9 wherein the pre-charging circuitry comprises masking circuitry, which, in operation, selectively masks outputs of columns of the array. ### Claim 11 (depends on 5) The memory array of claim 5 wherein the set of rows of bit-cells comprises a plurality of rows of bit cells and the set of rows of IMC cells comprises a plurality of rows of IMC cells. ### Claim 12 (depends on 11) The memory array of claim 11, comprising selection circuitry coupled to the set of rows of IMC cells, wherein the selection circuitry, in operation, selects a row of the plurality of rows of IMC cells. ### Claim 13 (depends on 11) The memory array of claim 11, wherein the set of rows of IMC cells comprises four rows of IMC cells. ### Claim 14 (depends on 12) The memory array of claim 12, wherein, in operation, individual rows of the set of rows of IMC cells are configurable to operate in an IMC mode of operation or in a bit-cell mode of operation. ### Claim 15 A system, comprising: a plurality of in-memory-compute (IMC) memory arrays, each IMC memory array including: a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns of the IMC memory array; and a plurality of in-memory-compute (IMC) cells of the IMC memory array arranged as a set of rows of IMC cells intersecting the plurality of columns of the IMC memory array, each of the IMC cells of the IMC memory array having: a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell; and accumulation circuitry coupled to the columns of the plurality of IMC memory arrays, wherein the first bit-cells of the IMC cells comprise a read-word line, and the second bit-cells of the IMC cells comprise a read-word line, and, in an in-memory-compute mode of operation of the system, the IMC cells selectively XOR data stored in the latches with data provided on the read-word lines. ### Claim 16 (depends on 15) The system of claim 15, wherein the plurality of bit-cells of the plurality of IMC memory arrays, the first bit-cells of the IMC cells, and the second bit-cells of the IMC cells are foundry bit-cells. ### Claim 17 (depends on 15) The system of claim 15, wherein the first bit-cells of the IMC cells comprise a read-bit line, and the second bit-cells of the IMC cells comprise a read-bit line, and, in the in-memory-compute mode of operation of the system, the IMC cells selectively XOR feature data stored in the latches with weight data provided on the read-word lines. ### Claim 18 A system, comprising: a plurality of in-memory-compute (IMC) memory arrays, each IMC memory array including: a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns of the IMC memory array; and a plurality of in-memory-compute (IMC) cells of the IMC memory array arranged as a set of rows of IMC cells intersecting the plurality of columns of the IMC memory array, each of the IMC cells of the IMC memory array having: a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell; and accumulation circuitry coupled to the columns of the plurality of IMC memory arrays, wherein the plurality of IMC memory arrays comprise pre-charging circuitry coupled to the plurality of IMC cells. ### Claim 19 (depends on 18) The system of claim 18 wherein the pre-charging circuitry comprises masking circuitry, which, in operation, selectively masks outputs of columns of the array. ### Claim 20 (depends on 15) The system of claim 15, wherein the accumulation circuitry comprises a plurality of adders. ### Claim 21 (depends on 15) The system of claim 15, wherein the accumulation circuitry comprises one or more capacitors. ### Claim 22 (depends on 21) The system of claim 21, comprising one or more bias capacitors selectively coupleable to the accumulation circuitry. ### Claim 23 (depends on 21) The system of claim 21, comprising readout circuitry coupled to the one or more capacitors. ### Claim 24 (depends on 23) The system of claim 23, wherein the readout circuitry comprises an analog-to-digital converter. ### Claim 25 (depends on 23) The system of claim 23, wherein the readout circuitry comprises a successive approximation circuit. ### Claim 26 A method, comprising: storing weight data in a plurality of rows of an in-memory-compute (IMC) memory array arranged as a plurality of rows of cells intersecting a plurality of columns of cells, the IMC memory array include a set of rows of bit-cells and a set of rows of IMC cells, wherein each of the IMC cells of the IMC memory array includes: a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell; storing feature data in one or more rows of the set of rows of IMC cells; and multiplying, using an IMC cell of a column of the IMC memory array, feature data stored in the IMC cell and weight data stored in the column of the IMC cell, wherein the first bit-cell of the IMC cell comprises a read-word line, and the second bit-cell of the IMC cell comprises a read-word line, and, the multiplying includes XORing data stored in the latches of the IMC cell with data provided on the read-word lines of the IMC cell. ### Claim 27 (depends on 26) The method of claim 26, comprising controlling an operation mode of individual rows of the set of rows of IMC cells. ### Claim 28 (depends on 26) The method of claim 26, wherein the multiplying is performed for a set of the plurality of columns and the method comprises accumulating multiplication results for the set of columns. ### Claim 29 (depends on 28) The method of claim 28, comprising accumulating multiplication results of a plurality of IMC memory arrays. ### Claim 30 (depends on 29) The method of claim 29, comprising applying a bias to the accumulated multiplication results. ### Claim 31 (depends on 29) The method of claim 29, comprising generating a classification signal of a neural network based on the accumulated multiplication results of the plurality of IMC memory arrays. ### Claim 32 A non-transitory computer-readable medium having contents, which, in operation, configure a computing system to perform a method, the method comprising: storing weight data in a plurality of rows of an in-memory-compute (IMC) memory array arranged as a plurality of rows of cells intersecting a plurality of columns of cells, the IMC memory array include a set of rows of bit-cells and a set of rows of IMC cells, wherein each of the IMC cells of the IMC memory array includes: a first bit-cell having a latch, a write-bit line and a complementary write-bit line; and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell; storing feature data in one or more rows of the set of rows of IMC cells; and multiplying, using an IMC cell of a column of the IMC memory array, feature data stored in the IMC cell and weight data stored in the column of the IMC cell, wherein the first bit-cell of the IMC cell comprises a read-word line, and the second bit-cell of the IMC cell comprises a read-word line, and, the multiplying includes XORing data stored in the latches of the IMC cell with data provided on the read-word lines of the IMC cell. ### Claim 33 (depends on 32) The non-transitory computer-readable medium of claim 32 wherein the contents comprise instructions executed by the computing system.