# US 12,183,421 B2 · Techniques for indicating row activation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,421 B2 - Document ID: US12183421B2 - Status: Granted - Kind: B2 - Application number: 18/408,228 - Filed: 2024-01-09 - Published: 2024-07-04 - Granted: 2024-12-31 - Earliest claimed: 2021-10-26 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Graziano Mirichigni; Efrem Bolandrina - Web page: https://patentgrep.com/patent/US12183421B2 ## CPC - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C 7/1042: {using interleaving techniques, i.e. read-write of one part of the memory while preparing another part} - G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising} - G11C 7/109: {Control signal input circuits} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 8/10: Decoders - G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command. ## Claims ### Claim 1 A method, comprising: transmitting a first activation command to open a first row of memory cells in a first subarray of a bank of a memory device; transmitting an indication of a second activation command for a second subarray of the bank based at least in part on transmitting the first activation command and before transmitting the second activation command; and transmitting the second activation command to open a second row of memory cells in the second subarray of the bank. ### Claim 2 (depends on 1) The method of claim 1, wherein the second subarray comprises the first subarray, the method further comprising: transmitting a read command an amount of time after transmitting the second activation command, the amount of time comprising a same section index shortened row address to column address delay (tRCD_SS) that is less than a default row address to column address delay (tRCD). ### Claim 3 (depends on 1) The method of claim 1, wherein the second subarray is different than the first subarray, the method further comprising: transmitting a read command an amount of time after transmitting the second activation command, the amount of time comprising a different section index shortened row address to column address delay (tRCD_DS) that is less than a default row address to column address delay (tRCD). ### Claim 4 (depends on 1) The method of claim 1, further comprising: transmitting, before transmitting the second activation command, a precharge command to close the first row of memory cells. ### Claim 5 (depends on 4) The method of claim 4, wherein the indication is transmitted in the precharge command. ### Claim 6 (depends on 4) The method of claim 4, wherein the second activation command is transmitted before the first row of memory cells in the first subarray of the bank is closed. ### Claim 7 (depends on 6) The method of claim 6, wherein the second activation command is transmitted an amount of time after the precharge command is transmitted, the amount of time comprising a shortened row precharge time (tRP_S) that is less than a default row precharge time (tRP). ### Claim 8 (depends on 1) The method of claim 1, further comprising: transmitting a second indication of a third activation command for a third subarray of the bank based at least in part on transmitting the second activation command and before transmitting the third activation command; and transmitting the third activation command to open a third row of memory cells in a fourth subarray of the bank, wherein the third subarray is different than the fourth subarray. ### Claim 9 (depends on 8) The method of claim 8, further comprising: transmitting a read command an amount of time after transmitting the third activation command, the amount of time comprising a default row address to column address delay (tRCD). ### Claim 10 (depends on 1) The method of claim 1, wherein the indication is transmitted in the first activation command. ### Claim 11 A host system, comprising: one or more controllers configured to cause the host system to: transmit a first activation command to open a first row of memory cells in a first subarray of a bank of a memory device; transmit an indication of a second activation command for a second subarray of the bank based at least in part on transmitting the first activation command and before transmitting the second activation command; and transmit the second activation command to open a second row of memory cells in the second subarray of the bank. ### Claim 12 (depends on 11) The host system of claim 11, wherein the second subarray comprises the first subarray, and wherein the one or more controllers are further configured to cause the host system to: transmit a read command an amount of time after transmitting the second activation command, the amount of time comprising a same section index shortened row address to column address delay (tRCD_SS) that is less than a default row address to column address delay (tRCD). ### Claim 13 (depends on 11) The host system of claim 11, wherein the second subarray is different than the first subarray, and wherein the one or more controllers are further configured to cause the host system to: transmitting a read command an amount of time after transmitting the second activation command, the amount of time comprising a different section index shortened row address to column address delay (tRCD_DS) that is less than a default row address to column address delay (tRCD). ### Claim 14 (depends on 11) The host system of claim 11, wherein the one or more controllers are further configured to cause the host system to: transmitting, before transmitting the second activation command, a precharge command to close the first row of memory cells. ### Claim 15 (depends on 14) The host system of claim 14, wherein the indication is transmitted in the precharge command. ### Claim 16 (depends on 14) The host system of claim 14, wherein the second activation command is transmitted before the first row of memory cells in the first subarray of the bank is closed. ### Claim 17 (depends on 16) The host system of claim 16, wherein the second activation command is transmitted an amount of time after the precharge command is transmitted, the amount of time comprising a shortened row precharge time (tRP_S) that is less than a default row precharge time (tRP). ### Claim 18 (depends on 11) The host system of claim 11, wherein the one or more controllers are further configured to cause the host system to: transmitting a second indication of a third activation command for a third subarray of the bank based at least in part on transmitting the second activation command and before transmitting the third activation command; and transmitting the third activation command to open a third row of memory cells in a fourth subarray of the bank, wherein the third subarray is different than the fourth subarray. ### Claim 19 (depends on 18) The host system of claim 18, wherein the one or more controllers are further configured to cause the host system to: transmitting a read command an amount of time after transmitting the third activation command, the amount of time comprising a default row address to column address delay (tRCD). ### Claim 20 A system, comprising: a memory device comprising one or more memory banks; a host device coupled with the memory device; and one or more controllers coupled with the host device and configured to: transmit a first activation command to open a first row of memory cells in a first subarray of a bank of the one or more memory banks; transmit an indication of a second activation command for a second subarray of the bank based at least in part on transmitting the first activation command and before transmitting the second activation command; and transmit the second activation command to open a second row of memory cells in the second subarray of the bank.