# US 12,183,419 B2 · Programmable column access

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- Number: US 12,183,419 B2
- Document ID: US12183419B2
- Status: Granted
- Kind: B2
- Application number: 17/648,403
- Filed: 2022-01-19
- Published: 2022-12-22
- Granted: 2024-12-31
- Earliest claimed: 2021-06-17
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hyunyoo Lee; Kang-Yong Kim; Taeksang Song
- Web page: https://patentgrep.com/patent/US12183419B2

## CPC

- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 7/08: Control thereof
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/109: {Control signal input circuits}
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 8/10: Decoders
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 11/2253: {Address circuits or decoders}
- G11C 11/2255: {Bit-line or column circuits}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/221: {using ferroelectric capacitors}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, systems, and devices for programmable column access are described. A device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. The voltages may be indicative of logic values stored at the memory cells. The device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. Each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer.

## Claims

### Claim 1

A method by a memory device, comprising:
transferring voltages from memory cells of a row in a memory array to respective digit lines for the memory cells, the voltages indicative of logic values stored at the memory cells;
communicating respective control signals concurrently to each respective multiplexer via a single selection line associated with the respective multiplexer of a set of multiplexers coupled with the digit lines, wherein each multiplexer is coupled with a respective subset of the digit lines and wherein each respective control signal is received at the respective multiplexer via the respective single selection line and comprises a numerical bit sequence indicating a single digit line of the respective subset of the digit lines based on each digit line of the respective subset of the digit lines being associated with a respective numerical bit sequence; and
coupling, concurrently by each multiplexer and based on the numerical bit sequence of the respective control signal for that multiplexer, a digit line of the respective subset of digit lines with a respective sense component for that multiplexer.

### Claim 2 (depends on 1)

The method of claim 1, wherein coupling comprises coupling a set of the digit lines with a set of sense components, the method further comprising:
sensing a respective logic state at each sense component of the set of sense components based on coupling the set of the digit lines with the set of sense components.

### Claim 3 (depends on 2)

The method of claim 2, wherein the set of the digit lines comprises digit lines associated with non-sequential column addresses.

### Claim 4 (depends on 1)

The method of claim 1, wherein communicating respective control signals comprises:
communicating a first control signal to a first multiplexer of the set of multiplexers, the first control signal having a first value; and
communicating a second control signal to a second multiplexer of the set of multiplexers, the second control signal having a second value different than the first value.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first control signal and the second control signal are communicated concurrently.

### Claim 6 (depends on 4)

The method of claim 4, wherein communicating respective control signals comprises:
communicating a third control signal to a third multiplexer of the set of multiplexers, the third control signal having a third value different than at least one of the first value or the second value.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
communicating a first control signal to a set of sense components comprising the respective sense components for each multiplexer; and
communicating a logic value sensed by a sense component of the set of sense components based on the first control signal.

### Claim 8 (depends on 1)

The method of claim 1, wherein each subset of digit lines comprises a unique plurality of digit lines associated with non-sequential column addresses.

### Claim 9 (depends on 1)

The method of claim 1, wherein coupling comprises coupling a first digit line with a first sense component, the method further comprising:
receiving, consecutively after a first activate address for the first digit line, a second activate address for a second digit line of the row;
coupling the second digit line with a second sense component based on the second activate address; and
communicating, over a data bus, a first logic value associated with the first digit line and a second logic value associated with the second digit line.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
receiving, consecutively after a first read command for the first digit line, a second read command for the second digit line, wherein the first logic value and the second logic value are communicated based on receiving the first read command and the second read command.

### Claim 11 (depends on 9)

The method of claim 9, wherein the control signals comprise a first control signal for a first multiplexer that is based on the first activate address, the method further comprising:
communicating a second control signal to a second multiplexer based on the second activate address, wherein the second digit line is coupled with the second sense component based on the second control signal.

### Claim 12

A memory device, comprising:
a memory array comprising a row of memory cells coupled with respective digit lines;
a controller coupled with the memory array and configured to concurrently communicate each respective control signal of a set of respective control signals to each respective multiplexer via a single selection line associated with the respective multiplexer of a set of multiplexers coupled with the digit lines, wherein each respective control signal is received at the respective multiplexer via the respective single selection line and comprises a numerical bit sequence indicating a single digit line of a subset of the digit lines coupled with the respective multiplexer based on each digit line of the subset of the digit lines being associated with a respective numerical bit sequence;
a first multiplexer of the set of multiplexers, that is coupled with the controller and a first subset of the digit lines, the first multiplexer configured to couple a first digit line of the first subset of the digit lines with a first sense component based on the numerical bit sequence of a first control signal of the set of respective control signals, wherein the first multiplexer couples the first digit line concurrently with a second multiplexer of the set of multiplexers; and
the second multiplexer of the set of multiplexers, coupled with the controller and a second subset of the digit lines, the second multiplexer configured to couple a second digit line of the second subset of the digit lines with a second sense component based on the numerical bit sequence of a second control signal of the set of respective control signals, wherein the second multiplexer couples the second digit line concurrently with the first multiplexer.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the first sense component is configured to sense a first logic state associated with the first digit line and the second sense component is configured to sense a second logic state associated with the second digit line.

### Claim 14 (depends on 12)

The memory device of claim 12, wherein the first control signal has a first value and the second control signal has a second value different than the first value.

### Claim 15 (depends on 12)

The memory device of claim 12, wherein the controller is configured to communicate the first control signal and the second control signal concurrently.

### Claim 16 (depends on 12)

The memory device of claim 12, further comprising:
a third multiplexer coupled with a third subset of the digit lines, the third multiplexer configured to couple a third digit line of the third subset with a third sense component based on a third control signal of the set of respective control signals.

### Claim 17

A memory device, comprising:
a memory array comprising a row of memory cells coupled with a set of multiplexers; and
one or more controllers coupled with the memory array and the set of multiplexers, the one or more controllers operable to cause the memory device to:
transfer voltages from memory cells of a row in the memory array to respective digit lines for the memory cells, the voltages indicative of logic values stored at the memory cells;
communicate respective control signals concurrently to each respective multiplexer via a single selection line associated with the respective multiplexer of the set of multiplexers, wherein each multiplexer is coupled with a respective subset of the digit lines and wherein each respective control signal is received at the respective multiplexer via the respective single selection line and comprises a numerical bit sequence indicating a single digit line of the respective subset of the digit lines based on each digit line of the respective subset of the digit lines being associated with a respective numerical bit sequence; and
couple, concurrently by each multiplexer and based on the numerical bit sequence of the control signal for that multiplexer, a digit line of the respective subset of digit lines with a sense component for that multiplexer.

### Claim 18 (depends on 17)

The memory device of claim 17, further comprising:
a set of sense components comprising a sense component for each multiplexer, the set of sense components configured to sense logic values associated with the digit lines.

### Claim 19 (depends on 17)

The memory device of claim 17, wherein the respective control signals comprise a first control signal communicated to a first multiplexer of the set of multiplexers and a second control signal communicated to a second multiplexer of the set of multiplexers.

### Claim 20 (depends on 19)

The memory device of claim 19, wherein the first control signal has a first value and the second control signal has a second value different than the first value.

### Claim 21 (depends on 19)

The memory device of claim 19, wherein the one or more controllers are configured to communicate the respective control signals concurrently.

### Claim 22 (depends on 19)

The memory device of claim 19, wherein the respective control signals comprise a third control signal communicated to a third multiplexer of the set of multiplexers and a fourth control signal communicated to a fourth multiplexer of the set of multiplexers.

### Claim 23 (depends on 17)

The memory device of claim 17, wherein the one or more controllers are configured to cause the memory device to couple a first digit line with a first sense component, and wherein the one or more controllers are further configured to cause the memory device to:
receive, consecutively after a first activate address for the first digit line, a second activate address for a second digit line of the row;
couple the second digit line with a second sense component based on the second activate address; and
communicate over a data bus a first logic value associated with the first digit line and a second logic value associated with the second digit line.

### Claim 24 (depends on 23)

The memory device of claim 23, wherein the one or more controllers are configured to cause the memory device to:
receive, consecutively after a first read command for the first digit line, a second read command for the second digit line, wherein the first logic value and the second logic value are communicated based on receiving the first and second read commands.