# US 12,183,418 B2 · Bank to bank data transfer

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- Number: US 12,183,418 B2
- Document ID: US12183418B2
- Status: Granted
- Kind: B2
- Application number: 17/985,304
- Filed: 2022-11-11
- Published: 2023-03-09
- Granted: 2024-12-31
- Earliest claimed: 2017-05-15
- Applicants: Lodestar Licensing Group LLC
- Inventors: Perry V. Lea; Troy A. Manning
- Web page: https://patentgrep.com/patent/US12183418B2

## CPC

- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine}
- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/408: Address circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- H03K 19/1733: {Controllable logic circuits (H03K19/177 takes precedence)}
- G11C 2207/002: Isolation gates, i.e. gates coupling bit lines to the sense amplifier
- G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
- G11C 2207/2236: Copy
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

## Claims

### Claim 1

A method, comprising:
determining that a program is running on a particular memory bank among a plurality of memory banks;
determining a data transfer path along a bank-to-bank transfer bus coupling the plurality of memory banks, wherein determining the data transfer path comprises determining a direction of travel with respect to the bank-to-bank transfer bus; and
causing data used by the program to be transferred from a different memory bank to the particular memory bank via the bank-to-bank transfer bus according to the data transfer path.

### Claim 2 (depends on 1)

The method of claim 1, wherein the program is a processing in memory program.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
transferring the data used by the program from the bank-to-bank transfer bus to the particular memory bank via at least one shared input/output (SIO) line.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
lines coupling respective memory banks among the plurality of memory banks to the bank-to-bank transfer bus and to logic comprising a plurality of latches via a plurality of shared input/output (SIO) lines, wherein the method further comprises:
transferring the data used by the program from the plurality of latches to the particular memory bank via at least one of the plurality of shared SIO lines.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
reconfiguring the bank-to-bank transfer bus to cause at least a portion of the data used by the program to be transferred from the different memory bank to the particular memory bank based, at least in part, on a location of the different memory bank with respect to the bank-to-bank transfer bus and the particular memory bank.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
causing the data used by the program to be transferred from the different memory bank to the particular memory bank via the bank-to-bank transfer bus according to the data transfer path in response to a user input.

### Claim 7

An apparatus, comprising:
a program running on a particular memory bank among a plurality of memory banks;
a bank-to-bank transfer bus; and
a controller, wherein the controller is configured to:
determine a data transfer path along the bank-to-bank transfer bus coupling the plurality of memory banks, wherein, to determine the data transfer path, the controller is configured to determine a direction of travel with respect to the bank-to-bank transfer bus; and
cause data used by the program to be transferred from a different memory bank to the particular memory bank via the bank-to-bank transfer bus according to the data transfer path.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the program is a processing in memory program.

### Claim 9 (depends on 7)

The apparatus of claim 7, wherein the bank-to-bank transfer bus comprises a ring architecture.

### Claim 10 (depends on 7)

The apparatus of claim 7, further comprising:
a plurality of shared input/output (SIO) lines coupling respective memory banks among the plurality of memory banks to the bank-to-bank transfer bus, wherein the controller is further configured to:
transfer the data used by the program from the bank-to-bank transfer bus to the particular memory bank via at least one SIO line among the plurality of shared SIO lines.

### Claim 11 (depends on 7)

The apparatus of claim 7, further comprising:
a plurality of shared input/output (SIO) lines coupling respective memory banks among the plurality of memory banks to the bank-to-bank transfer bus; and
a plurality of latches coupled to the plurality of memory banks, wherein the controller is further configured to:
control transfer of the data used by the program from the plurality of latches to the particular memory bank via at least one of the plurality of shared SIO lines.

### Claim 12 (depends on 7)

The apparatus of claim 7, wherein the controller is further configured to:
reconfigure the bank-to-bank transfer bus to cause at least a portion of the data used by the program to be transferred from the different memory bank to the particular memory bank based, at least in part, on a location of the different memory bank with respect to the bank-to-bank transfer bus and the particular memory bank.

### Claim 13 (depends on 7)

The apparatus of claim 7, wherein the controller is further configured to:
receive a user input; and
cause the data used by the program to be transferred from the different memory bank to the particular memory bank via the bank-to-bank transfer bus according to the data transfer path in response to the user input.

### Claim 14

A system, comprising:
a host; and
a memory device coupled to the host, the memory device comprising:
a program running on a particular memory bank among a plurality of memory banks associated with the memory device;
a bank-to-bank transfer bus; and
a controller, wherein the controller is configured to:
receive a command from the host to initiate an operation associated with the program;
determine a data transfer path along the bank-to-bank transfer bus in response to receipt of the command from the host, wherein, to determine the data transfer path, the controller is configured to determine a direction of travel with respect to the bank-to-bank transfer bus; and
cause data used by the program to be transferred between a different memory bank and the particular memory bank via the bank-to-bank transfer bus according to the data transfer path.

### Claim 15 (depends on 14)

The system of claim 14, wherein the controller is further configured to:
cause the data used by the program to be transferred to the different memory bank from the particular memory bank via the bank-to-bank transfer bus according to the data transfer path.

### Claim 16 (depends on 14)

The system of claim 14, wherein the controller is further configured to:
cause the data used by the program to be transferred from the different memory bank to the particular memory bank via the bank-to-bank transfer bus according to the data transfer path.

### Claim 17 (depends on 14)

The system of claim 14, wherein the program is a processing in memory program.