# US 12,183,415 B2 · Memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,183,415 B2
- Document ID: US12183415B2
- Status: Granted
- Kind: B2
- Application number: 18/203,717
- Filed: 2023-05-31
- Published: 2023-09-28
- Granted: 2024-12-31
- Earliest claimed: 2017-06-27
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Tatsuya Onuki; Shuhei Nagatsuka
- Web page: https://patentgrep.com/patent/US12183415B2

## CPC

- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 11/4094: Bit-line management or control circuits
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/08: Control thereof
- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 11/403: with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

## Claims

### Claim 1

A semiconductor device comprising:
a first layer; and
a second layer over the first layer,
wherein a memory cell comprises a first transistor and a capacitor;
wherein a switch comprises a third transistor;
wherein one of a source and a drain of the first transistor is electrically connected to the capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to a sense amplifier through the switch,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of a second transistor,
wherein the gate of the second transistor is electrically connected to one of a source and a drain of the second transistor through the switch,
wherein one of a source and a drain of the third transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the one of the source and the drain of the second transistor,
wherein the first layer comprises the switch, the second transistor, and the sense amplifier, and
wherein the second layer comprises the memory cell.

### Claim 2

A semiconductor device comprising:
a first layer; and
a second layer over the first layer,
wherein the second layer comprises a memory cell comprising a first transistor and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein the first layer comprises a second transistor and a third transistor,
wherein a gate of the second transistor is electrically connected to the first wiring, and
wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2,
wherein the first layer comprises a sense amplifier.