# US 12,183,410 B2 · Data storage apparatus comprising cell section operable as dosimeter and method of operating > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,410 B2 - Document ID: US12183410B2 - Status: Granted - Kind: B2 - Application number: 18/248,542 - Filed: 2021-10-13 - Published: 2023-11-30 - Granted: 2024-12-31 - Earliest claimed: 2020-10-14 - Assignees: ams International AG - Applicants: ams International AG - Inventors: Tommaso Vincenzi; Gregor Schatzberger - Web page: https://patentgrep.com/patent/US12183410B2 ## CPC - G11C 7/14: Dummy cell management; Sense reference voltage generators - G11C 29/022: {in I/O circuitry} - G11C 7/08: Control thereof - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 2029/0409: {Online test} - G11C 2029/5006: {Current} - G11C 2207/2254: Calibration - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A data storage apparatus includes an integrated circuit further including a control unit and a memory array of charge-based memory cells. The memory array includes a first subsection which is operable as a memory, and includes a second subsection which is operable as a dosimeter. The control unit is operable to provide a reference current and to conduct memory access operations to access the memory with reference to the reference current. The control unit is further operable to analyze a statistical distribution of read currents by using memory access operations in the second subsection. Said analysis involves counting of logical read errors of the memory access operations and calibrating the reference current depending on a number of counted logical read errors being indicative also of a Total Ionizing Dose, TID. ## Claims ### Claim 1 A data storage apparatus, comprising an integrated circuit further comprising a control unit and a memory array of charge-based memory cells, wherein: the memory array comprises a first subsection which is operable as a memory, and comprises a second subsection which is operable as a dosimeter; the control unit is operable to provide a reference current and to conduct memory access operations to access the memory with reference to the reference current; and the control unit is further operable to analyze a statistical distribution of read currents by using memory access operations in the second subsection, wherein said analysis involves: counting of logical read errors of the memory access operations, and calibrating the reference current depending on a number of counted logical read errors being indicative also of a Total Ionizing Dose, TID. ### Claim 2 (depends on 1) The apparatus according to claim 1, further comprising a column control block operable for memory access operations and comprising comparators, and wherein during said memory access operations the comparators are operable to compare read currents with the reference current. ### Claim 3 (depends on 2) The apparatus according to claim 2, wherein: the comparators comprise current sense amplifiers configured in a single-ended or in a differential structure, and the current sense amplifiers are operable to compare read currents with the reference current, and/or the column control block further comprises a data buffer and a bitline driver, a row control block (300) comprises a wordline driver. ### Claim 4 (depends on 2) The apparatus according to claim 2, wherein the control block comprises: a counter to analyze the statistical distribution of read currents in the second subsection as a function of a number of memory cells, wherein the analysis involves: using the current sense amplifiers, successively comparing read currents from the statistical distribution of read currents with the reference current, generating for each comparison a logic TRUE or FALSE signal if said comparison meets a comparison criterion or not, and counting the number of logical FALSE signals as number of counted logical read errors. ### Claim 5 (depends on 1) The apparatus according to claim 1, wherein the control block is operable to analyze the statistical distribution of read currents by executing the following steps: storing data in the memory array by writing first storage values to the charge-based memory cells of the second subsection, reading second storage values from the charge-based memory cells of the second subsection, respectively, and counting the number of charge-based memory cells of the second subsection which return logical FALSE signals, thus indicating a read current being higher than the reference current and indicating a logical read error. ### Claim 6 (depends on 5) The apparatus according to claim 5, wherein the control block is operable of calibrating the reference current as a function the number of counted logical read errors and performing a memory access operation on the memory cells using the calibrated reference current as reference current. ### Claim 7 (depends on 1) The apparatus according to claim 1, wherein a number of charge-based memory cells of the first subsection is larger than a number of charge-based memory cells of the second subsection. ### Claim 8 (depends on 1) The apparatus according to claim 1, wherein the second subsection comprises at least one block of memory cells having a same programming, where said same programming corresponds to the programming of the memory cells of the first subsection. ### Claim 9 (depends on 8) The apparatus according to claim 8, wherein the control block is operable to, at least for the block of same programming, determine from the read currents a number of errors as a measure of the Total Ionizing Dose, TID. ### Claim 10 (depends on 1) The apparatus according to claim 1, wherein the second subsection is sub-divided into blocks of memory cells of different pre-charge conditions, and each block has a different pulse time for programming, respectively. ### Claim 11 (depends on 10) The apparatus according to claim 10, wherein N denotes the total number of charge-based memory cells of the first subsection, parameter a denotes a fraction of the total number of charge-based memory cells comprised by the second subsection and M denotes a number of blocks in the second subsection, and wherein: N · a M ≥ 2 ⁢ 0 ⁢ 0 . ### Claim 12 (depends on 1) The apparatus according to claim 1, wherein memory cells comprised by the second subsection are never reprogrammed after the first preparation of said subsection, in particular, programmed with a specific pulse time. ### Claim 13 (depends on 1) An electronic device, comprising a data storage apparatus according to claim 1 and a host system, including at least one of: a medical device, an aeronautics device, a high energy physics detector, an integrated wear-controlled space device, a portable mobile device for personal use, a portable detector for food radioactivity, or a portable detector for checking surrounding radioactive activity. ### Claim 14 A method of operating a data storage apparatus, the apparatus comprising an integrated circuit having a control unit and a memory array of charge-based memory cells, wherein the memory array comprises a first subsection which is operable as a memory, and comprises a second subsection of charge-based memory cells which is operable as a dosimeter; the method comprising: using the control unit, providing a reference current, conducting memory access operations to access the memory with reference to the reference current to analyze a statistical distribution of read currents, counting logical read errors of the memory access operations in the second subsection, calibrating the reference current depending on a number of counted logical read errors being indicative also of a Total Ionizing Dose, TID. ### Claim 15 (depends on 14) The method according to claim 14, comprising the further steps of: programming the memory with various pulse time or pre-charge conditions by writing first storage values to the charge-based memory cells of the second subsection and/or erasing data in the memory array, reading second storage values from the memory cells of the second subsection with reference to the reference current and counting the logical errors being indicative of a first reference condition, reading second storage values from the memory cells of the second subsection with reference to at least one intermediate reference current and counting the logical errors being indicative of a second reference condition, comparing the number of logical errors for the first and at least the second reference condition, and calibrating the reference current such that the reference current with the smaller number of logical errors is set as reference current.