# US 12,183,406 B2 · Eliminating write disturb for system metadata in a memory sub-system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,406 B2 - Document ID: US12183406B2 - Status: Granted - Kind: B2 - Application number: 18/238,850 - Filed: 2023-08-28 - Published: 2023-12-14 - Granted: 2024-12-31 - Earliest claimed: 2021-08-25 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Tingjun Xie; Zhenming Zhou; Zhenlei Shen; Charles See Yeung Kwong - Web page: https://patentgrep.com/patent/US12183406B2 ## CPC - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 7/02: with means for avoiding parasitic signals - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 29/76: {using address translation or modifications} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2029/0411: {Online error correction} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract It is determined whether a write disturb capability associated with a first location of a memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of memory units is remapped to a second location of the memory device, wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion. ## Claims ### Claim 1 A system comprising: a memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising: determining that a write disturb capability associated with a first location of the memory device satisfies a threshold criterion; and responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, remapping a plurality of memory units residing in the first location to a second location of the memory device, wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion. ### Claim 2 (depends on 1) The system of claim 1, wherein to remap the plurality of memory units to the second location of the memory device, the processing device is to perform operations comprising: identifying each logical address of a plurality of logical addresses associated with the plurality of memory units in a corresponding entry of a plurality of entries of a data structure associated with the memory device; determining that each logical address is associated with the first location of the memory device in the entry of the data structure; and responsive to determining that each logical address is associated with the first location of the memory device in the entry of the data structure, updating the entry of the data structure, wherein updating the entry of the data structure comprises associating each logical address with the second location of the memory device. ### Claim 3 (depends on 1) The system of claim 1, wherein to determine that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, the processing device is to perform operations comprising: determining that a memory unit residing in the first location of the memory device is associated with a data quality degradation in response to a threshold number of write disturb attacks. ### Claim 4 (depends on 1) The system of claim 1, wherein the processing device is to perform operations further comprising: determining that the write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion, wherein determining that the write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion comprises determining that a memory unit residing in the second location of the memory device is not associated with a data quality degradation in response to a threshold number of write disturb attacks. ### Claim 5 (depends on 1) The system of claim 1, wherein each memory unit of the plurality of memory units comprises one or more memory cells storing system metadata associated with the memory device. ### Claim 6 (depends on 1) The system of claim 1, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers, wherein the plurality of layers comprises a plurality of decks of the memory device, wherein the first location of the plurality of memory units corresponds to a first deck of the plurality of decks where the plurality of memory units is located, and wherein the second location of the plurality of memory units corresponds to a second deck of the plurality of decks where the plurality of memory units is located. ### Claim 7 A method comprising: determining that a write disturb capability associated with a first location of a memory device satisfies a threshold criterion; and responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, remapping a plurality of memory units residing in the first location to a second location of the memory device, wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion. ### Claim 8 (depends on 7) The method of claim 7, wherein remapping the plurality of memory units to the second location of the memory device comprises: identifying each logical address of a plurality of logical addresses associated with the plurality of memory units in a corresponding entry of a plurality of entries of a data structure associated with the memory device; determining that each logical address is associated with the first location of the memory device in the entry of the data structure; and responsive to determining that each logical address is associated with the first location of the memory device in the entry of the data structure, updating the entry of the data structure, wherein updating the entry of the data structure comprises associating each logical address with the second location of the memory device. ### Claim 9 (depends on 7) The method of claim 7, wherein determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion comprises determining that a memory unit residing in the first location of the memory device is associated with a data quality degradation in response to a threshold number of write disturb attacks. ### Claim 10 (depends on 7) The method of claim 7, further comprising: determining that the write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion, wherein determining that the write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion comprises determining that a memory unit residing in the second location of the memory device is not associated with a data quality degradation in response to a threshold number of write disturb attacks. ### Claim 11 (depends on 7) The method of claim 7, wherein each memory unit of the plurality of memory units comprises one or more memory cells storing system metadata associated with the memory device. ### Claim 12 (depends on 7) The method of claim 7, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers, wherein the plurality of layers comprises a plurality of decks of the memory device, wherein the first location of the plurality of memory units corresponds to a first deck of the plurality of decks where the plurality of memory units is located, and wherein the second location of the plurality of memory units corresponds to a second deck of the plurality of decks where the plurality of memory units is located. ### Claim 13 A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: determining that a write disturb capability associated with a first location of a memory device satisfies a threshold criterion; and responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, remapping a plurality of memory units residing in the first location to a second location of the memory device, wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion. ### Claim 14 (depends on 13) The non-transitory computer-readable storage medium of claim 13, wherein to remap the plurality of memory units to the second location of the memory device, the processing device is to perform operations comprising: identifying each logical address of a plurality of logical addresses associated with the plurality of memory units in a corresponding entry of a plurality of entries of a data structure associated with the memory device; determining that each logical address is associated with the first location of the memory device in the entry of the data structure; and responsive to determining that each logical address is associated with the first location of the memory device in the entry of the data structure, updating the entry of the data structure, wherein updating the entry of the data structure comprises associating each logical address with the second location of the memory device. ### Claim 15 (depends on 13) The non-transitory computer-readable storage medium of claim 13, wherein to determine that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, the processing device is to perform operations comprising: determining that a memory unit residing in the first location of the memory device is associated with a data quality degradation in response to a threshold number of write disturb attacks. ### Claim 16 (depends on 13) The non-transitory computer-readable storage medium of claim 13, wherein the processing device is to perform operations further comprising: determining that the write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion, wherein determining that the write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion comprises determining that a memory unit residing in the second location of the memory device is not associated with a data quality degradation in response to a threshold number of write disturb attacks. ### Claim 17 (depends on 13) The non-transitory computer-readable storage medium of claim 13, wherein each memory unit of the plurality of memory units comprises one or more memory cells storing system metadata associated with the memory device. ### Claim 18 (depends on 13) The non-transitory computer-readable storage medium of claim 13, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device, and wherein the second location of the memory device corresponds to a second layer of the plurality of layers. ### Claim 19 (depends on 18) The non-transitory computer-readable storage medium of claim 18, wherein the plurality of layers comprises a plurality of decks of the memory device, wherein the first location of the plurality of memory units corresponds to a first deck of the plurality of decks where the plurality of memory units is located, and wherein the second location of the plurality of memory units corresponds to a second deck of the plurality of decks where the plurality of memory units is located. ### Claim 20 (depends on 13) The non-transitory computer-readable storage medium of claim 13, wherein the processing device is to perform operations further comprising: identifying the plurality of memory units residing in the first location of the memory device, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device.