# US 12,183,405 B2 · Semiconductor memory device and memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,405 B2 - Document ID: US12183405B2 - Status: Granted - Kind: B2 - Application number: 17/899,014 - Filed: 2022-08-30 - Published: 2023-10-05 - Granted: 2024-12-31 - Earliest claimed: 2022-03-30 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Mitsuhiro Abe; Yasuhiro Hirashima; Mitsuaki Honma - Web page: https://patentgrep.com/patent/US12183405B2 ## CPC - G11C 16/32: Timing circuits - H10W 90/00: Package configurations - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot. ## Claims ### Claim 1 A semiconductor memory device comprising: a first pad; a clock generation circuit configured to generate a first clock, wherein the clock generation circuit includes an oscillator, and a frequency divider configured to divide a frequency of an output of the oscillator to generate the first clock; a memory that stores first information indicating a total number of time slots, second information indicating which of the time slots should be designated as a designated time slot, and third information designating the semiconductor memory device as either a leader or a follower; an output circuit configured to output the first clock through the first pad; a designation circuit configured to count clock cycles of the first clock and designate one of the time slots as the designated time slot based on a count of the clock cycles, the first information, and the second information; and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot, wherein the output circuit is operational when the semiconductor memory device is designated as the leader, and is not operational when the semiconductor memory device is designated as the follower. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein each time slot corresponds to one clock cycle of the first clock in each of a plurality of groups of contiguous clock cycles of the first clock, that are contiguous with one another. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the clock generation circuit, the output circuit, the designation circuit, and the peak control circuit operate in response to a peak control start command. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein the designation circuit is configured to output a peak enable signal at the timing corresponding to the designated time slot to the peak control circuit, and the peak control circuit is configured to execute the operation in response to the receipt of the peak enable signal from the designation circuit. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the first, second, and third information are retrieved from a read-only-memory area of the semiconductor memory device. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, wherein the first, second, and third information are received through additional pads of the semiconductor memory device from a memory controller connectable to the semiconductor memory device. ### Claim 7 (depends on 6) The semiconductor memory device according to claim 6, wherein the first information is received with a command that does not include a chip address, and the second and third information are received with a command that includes a chip address. ### Claim 8 A memory system comprising: a plurality of semiconductor memory devices, each including a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous time slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot; and a memory controller configured to control the plurality of semiconductor memory devices. ### Claim 9 (depends on 8) The memory system according to claim 8, wherein the output circuit of one of the plurality of semiconductor memory devices is operational and the output circuit of each of the other semiconductor memory devices is not operational. ### Claim 10 (depends on 9) The memory system according to claim 9, wherein the first pad of each of the plurality of semiconductor memory devices is electrically connected together through bonding wires. ### Claim 11 (depends on 10) The memory system according to claim 10, wherein the clock generation circuit in each of the semiconductor memory devices includes an oscillator, and a frequency divider configured to divide a frequency of an output of the oscillator to generate the first clock, and the first clock is shared among the plurality of semiconductor memory devices through the first pads of the plurality of semiconductor memory devices. ### Claim 12 (depends on 11) The memory system according to claim 11, wherein one of the plurality of semiconductor memory devices supplies the first clock generated by the clock generation circuit thereof to the designation circuit therein, and each of the other semiconductor memory devices receives the first clock through the first pad thereof and supplies the received first clock to the designation circuit therein. ### Claim 13 (depends on 12) The memory system according to claim 12, wherein the memory controller issues a command to said one of the plurality of semiconductor memory devices to be a leader, and issues a command to said each of the other semiconductor memory devices to be a follower. ### Claim 14 (depends on 12) The memory system according to claim 12, wherein each of the plurality of semiconductor memory devices includes a read-only-memory that stores information designating the semiconductor memory device to be a leader or a follower, and said one of the plurality of semiconductor memory devices is designated as the leader in the information stored in the read-only-memory thereof, and said each of the other semiconductor memory devices is designated as the follower in the information stored in the read-only-memory thereof. ### Claim 15 (depends on 8) The memory system according to claim 8, wherein each time slot corresponds to one clock cycle of the first clock in each of a plurality of groups of contiguous clock cycles of the first clock, that are contiguous with one another. ### Claim 16 (depends on 8) The memory system according to claim 8, wherein a total number of the plurality of contiguous time slots is equal to a total number of the plurality of semiconductor memory devices, and the designated time slots of the plurality of semiconductor memory devices are different. ### Claim 17 (depends on 10) The memory system according to claim 10, wherein the first pad is a write protection signal control pad.