# US 12,183,404 B2 · Clock signal return scheme for data read in page buffer of memory device

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- Number: US 12,183,404 B2
- Document ID: US12183404B2
- Status: Granted
- Kind: B2
- Application number: 18/197,526
- Filed: 2023-05-15
- Published: 2023-09-07
- Granted: 2024-12-31
- Earliest claimed: 2021-04-28
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Shu Xie
- Web page: https://patentgrep.com/patent/US12183404B2

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 7/1066: {Output synchronization}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/32: Timing circuits
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 11/5621: {using charge storage in a floating gate}
- G11C 11/5671: {using charge trapping in an insulator}
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/35: with cell select transistors, e.g. NAND
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

In certain aspects, a memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array. The peripheral circuit includes frequency dividers and a clock path coupled to the frequency dividers. Each of the frequency dividers is configured to receive a clock signal and generate a clock return signal. The clock return signal corresponds to the clock signal. A period of the clock return signal is greater than the period of the clock signal. The clock path is configured to merge the clock return signals.

## Claims

### Claim 1

A memory device, comprising:
a memory cell array; and
a peripheral circuit coupled to the memory cell array the peripheral circuit comprising:
frequency dividers, each of the frequency dividers being configured to receive a clock signal and generate a clock return signal, the clock return signal corresponding to the clock signal, a period of the clock return signal being greater than the period of the clock signal;
a first clock level set module coupled to one of the frequency dividers, and configured to determine the clock return signal based on an address associated with the clock signal; and
a clock path coupled to the frequency dividers and configured to merge the clock return signals.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the first clock level set module is further configured to determine a start level of the clock return signal based on an address associated with the clock signal.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein
the peripheral circuit further comprises a second clock level set module;
the first clock level set module coupled to a first frequency divider of the frequency dividers; and
the second clock level set module coupled to a second frequency divider of the frequency dividers.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the clock path configured to merge the clock return signals by an OR operation or an AND operation.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein
the peripheral circuit further comprises a first delay circuit coupled to the first frequency divider; and
the first delay circuit is configured to synchronize a first clock return signal output by the first frequency divider with a corresponding data signal.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the clock path comprises:
first portions of the clock path, each of the first portions of the clock path being configured to merge two of the clock return signals to obtain a merged clock return signal; and
a second portion of the clock path coupled to the first portions of the clock path and configured to merge the merged clock return signals.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein
the first portions of the clock path comprise a NOR gate and a NOT gate coupled to the NOR gate; and
the second portion of the clock path comprises a NOR gate and a NOT gate coupled to the NOR gate.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the first clock level set module comprises:
an address circuit configured to determine a parity of number of cycles in the clock signal based on the address associated with the clock signal; and
an SR circuit configured to set a start level of the clock return signal based on the parity.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein
each of the frequency dividers comprises a flip-flop coupled to the clock path;
the flip-flop comprises a clock input receiving the clock signal and a first output outputting the clock return signal; and
an inverter coupled to the clock input and a second output of the flip-flop.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein a duty cycle of the clock return signal is 50%.

### Claim 11

A system, comprising:
a memory device comprising a memory cell array, and a peripheral circuit coupled to the memory cell array, the peripheral circuit comprising:
frequency dividers, each of the frequency dividers being configured to receive a clock signal and generate a clock return signal, the clock return signal corresponding to the clock signal, a period of the clock return signal is greater than the period of the clock signal;
a first clock level set module coupled to one of the frequency dividers, and configured to determine the clock return signal based on an address associated with the clock signal; and
a clock path coupled to the frequency dividers and configured to merge the clock return signals.

### Claim 12 (depends on 11)

The system of claim 11, further comprising a memory controller coupled to the memory device and configured to provide a read instruction to the peripheral circuit.

### Claim 13 (depends on 12)

The system of claim 12, wherein the address is in the read instruction provided by the memory controller.

### Claim 14

A method for operating a memory device, the method comprising:
receiving a first clock signal of clock signals;
generating a first clock return signal of clock return signals corresponding to the first clock signal, wherein a period of the first clock return signal is greater than the period of the first clock signal;
receiving a read instruction;
obtaining an address in the read instruction; and
setting a start level of the first clock return signal based on the address.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
determining a parity of number of cycles in the first clock signal based on the address associated with the first clock signal; and
setting the start level of the first clock return signal based on the parity.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
setting a start level of a second clock return signal signals corresponding to a second clock return signal to be a same level as an end level of the first clock return signal, wherein the second clock return signal is returned next to the first clock return signal.

### Claim 17 (depends on 14)

The method of claim 14, further comprising merging the clock return signals.

### Claim 18 (depends on 11)

The system of claim 11, wherein the clock path configured to merge the clock return signals by an OR operation or an AND operation.

### Claim 19 (depends on 11)

The system of claim 11, wherein the clock path comprises:
first portions of the clock path, each of the first portions of the clock path being configured to merge two of the clock return signals to obtain a merged clock return signal; and
a second portion of the clock path coupled to the first portions of the clock path and configured to merge the merged clock return signals.

### Claim 20 (depends on 11)

The system of claim 11, wherein the first clock level set module comprises:
an address circuit configured to determine a parity of number of cycles in the clock signal based on the address associated with the clock signal; and
an SR circuit configured to set a start level of the clock return signal based on the parity.