# US 12,183,403 B2 · Three-dimensional memory device and improved methods of reading the same by shortening read times

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- Number: US 12,183,403 B2
- Document ID: US12183403B2
- Status: Granted
- Kind: B2
- Application number: 18/156,955
- Filed: 2023-01-19
- Published: 2023-05-18
- Granted: 2024-12-31
- Earliest claimed: 2021-02-09
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Siyuan Wang; Jin Yong Oh; Yu Wang; Ye Tian; Zhichao Du; Xiaojiang Guo
- Web page: https://patentgrep.com/patent/US12183403B2

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 16/32: Timing circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.

## Claims

### Claim 1

A method for reading a memory device, the method comprising:
applying a first bit line voltage to a first selected bit line;
applying a second bit line voltage to a second selected bit line;
applying a first read voltage to a word line to determine whether a first selected memory cell coupled to the word line is at a first data state, wherein the first selected memory cell is coupled to the first selected bit line;
in response to the determining that first selected memory cell is at the first data state, maintaining the first bit line voltage at the first selected bit line; and
applying a second read voltage to the word line while maintaining the first bit line voltage at the first selected bit line to determine whether a second selected memory cell coupled to the word line is at a second data state, wherein the second selected memory cell is coupled to the second selected bit line.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
performing two or more read operations for the first and second selected memory cells in a same page, each of the first and second selected memory cells configured to have two or more data states, wherein a first read operation comprises the applying of the first read voltage and a second read operation comprises the maintaining of the first bit line voltage and the applying of the second read voltage.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first data state corresponds to a first threshold voltage of the first selected memory cell, which is lower than a second threshold voltage corresponding to the second data state; and wherein the second read voltage is higher than the first read voltage.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
discharging corresponding bit lines only after all selected memory cells in the same page have been read.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second bit line voltage is higher than the first bit line voltage.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first bit line voltage is larger than half voltage level of the second bit line voltage.

### Claim 7

A method for reading a memory device that includes memory cells each having two or more data states, the method comprising:
performing a first read operation, comprising:
applying a first bit line voltage to a first selected bit line; and
applying a first read voltage to a word line to determine whether a first selected memory cell coupled to the word line and the first selected bit line is at a first data state; and
performing a second read operation, comprising:
maintaining the first bit line voltage at the first selected bit line associated with the first selected memory cell which is determined to be at the first data state;
applying a second read voltage to the word line while maintaining the first bit line voltage at the first selected bit line to determine whether a second selected memory cell coupled to the word line is at a second data state; and
applying a second bit line voltage to a second selected bit line associated with the second selected memory cell, wherein the second bit line voltage is higher than the first bit line voltage.

### Claim 8 (depends on 7)

The method of claim 7, wherein:
the first and second selected memory cells are in a same page;
the first data state corresponds to a first threshold voltage of the first selected memory cell, which is lower than a second threshold voltage corresponding to the second data state; and
the second read voltage is higher than the first read voltage.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
discharging corresponding bit lines only after all selected memory cells in the same page have been read.

### Claim 10 (depends on 7)

The method of claim 7, wherein the first bit line voltage is larger than half voltage level of the second bit line voltage.

### Claim 11 (depends on 7)

The method of claim 7, wherein the performing of the first read operation further comprises:
applying the second bit line voltage to the first selected bit line; and
determining that the first selected memory cell is at the first data state when the second bit line voltage is lowered to the first bit line voltage that is below a predetermined value.

### Claim 12

A three-dimensional (3D) memory device, comprising:
memory cells each configured to have two or more data states and addressable through a word line and a bit line;
a page buffer for sensing a voltage level of a respective bit line; and
a control circuit configured to:
apply a first bit line voltage to a first selected bit line;
apply a second bit line voltage to a second selected bit line, wherein the second bit line voltage is different from the first bit line voltage;
apply a first read voltage to the word line to determine whether a first selected memory cell coupled to the word line and the first selected bit line is at a first data state;
in response to the first selected memory cell being at the first data state, maintain the first bit line voltage at the first selected bit line; and
apply a second read voltage to the word line while the first bit line voltage is maintained at the first selected bit line to determine whether a second selected memory cell coupled to the word line and the second selected bit line is at a second data state.

### Claim 13 (depends on 12)

The 3D memory device of claim 12, wherein the control circuit is further configured to perform two or more read operations for the first and second selected memory cells in a same page, wherein a first read operation comprises the applying of the first read voltage and a second read operation comprises the maintaining of the first bit line voltage and the applying of the second read voltage.

### Claim 14 (depends on 13)

The 3D memory device of claim 13, wherein the control circuit is further configured to discharge corresponding bit lines only after all selected memory cells in the same page have been read.

### Claim 15 (depends on 12)

The 3D memory device of claim 12, wherein the first data state corresponds to a first threshold voltage of the first selected memory cell, which is lower than a second threshold voltage corresponding to the second data state; and wherein the second read voltage is higher than the first read voltage.

### Claim 16 (depends on 12)

The 3D memory device of claim 12, wherein the second bit line voltage is higher than the first bit line voltage.

### Claim 17 (depends on 16)

The 3D memory device of claim 16, wherein the first bit line voltage is larger than half voltage level of the second bit line voltage.