# US 12,183,401 B2 · Semiconductor storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,401 B2 - Document ID: US12183401B2 - Status: Granted - Kind: B2 - Application number: 18/480,305 - Filed: 2023-10-03 - Published: 2024-01-25 - Granted: 2024-12-31 - Earliest claimed: 2021-02-02 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hiroyuki Takenaka; Akihiko Chiba; Teppei Higashitsuji; Kiyofumi Sakurai; Hiroaki Nakasa; Youichi Magome - Web page: https://patentgrep.com/patent/US12183401B2 ## CPC - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/30: Power supply circuits - G11C 16/08: Address circuits; Decoders; Word-line control circuits - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line. ## Claims ### Claim 1 A storage device comprising a first substrate having a first active region; a second substrate having a second active region, the second substrate provided above the first substrate in a first direction orthogonal to a surface of the first substrate; a first memory cell transistor provided between the first substrate and the second substrate in the first direction; a first word line electrically connected to a gate of the first memory cell transistor; a first bit line electrically connected to a drain of the first memory cell transistor; a first transistor having a channel region in the first active region, the first transistor configured to control supply of a voltage to the gate of the first memory cell transistor through the first word line; and a sense amplifier having a channel region in the second active region, the sense amplifier configured to control supply of a voltage to the drain of the first memory cell transistor through the first bit line, wherein the first substrate, the first memory cell transistor, the first word line, and the first transistor are provided in a first chip, the second substrate and the sense amplifier are provided in a second chip, and the second chip is provided above the first chip in the first direction. ### Claim 2 (depends on 1) The storage device of claim 1, further comprising: a second memory cell transistor provided between the first substrate and the second substrate in the first direction; and a first contact provided between the first memory cell transistor and the second memory cell transistor in a second direction perpendicular to the first direction, wherein the first transistor is electrically connected to the gate of the first memory cell transistor through the first contact and the first word line. ### Claim 3 (depends on 1) The storage device of claim 1, further comprising: a second memory cell transistor provided between the first substrate and the second substrate in the first direction; a second word line electrically connected to a gate of the second memory cell transistor; and a second transistor having a channel region in the second active region, the second transistor configured to control supply of a voltage to the gate of the second memory cell transistor through the second word line. ### Claim 4 (depends on 3) The storage device of claim 3, further comprising: a first contact provided between the first memory cell transistor and the second memory cell transistor in a second direction perpendicular to the first direction; and a second contact provided between the first memory cell transistor and the second memory cell transistor in the second direction, wherein the first transistor is electrically connected to the gate of the first memory cell transistor through the first contact and the first word line, and the second transistor is electrically connected to the gate of the second memory cell transistor through the second contact and the second word line. ### Claim 5 (depends on 1) The storage device of claim 1, further comprising: a capacitor provided adjacent to the first transistor in a second direction perpendicular to the first direction. ### Claim 6 (depends on 5) The storage device of claim 5, wherein the sense amplifier is disposed above the capacitor in the first direction. ### Claim 7 A device comprising: a first substrate having a first active region; a second substrate having a second active region, the second substrate provided above the first substrate in a first direction orthogonal to a surface of the first substrate; a first memory cell transistor provided between the first substrate and the second substrate in the first direction; a second memory cell transistor provided between the first substrate and the second substrate in the first direction; a first contact provided between the first memory cell transistor and the second memory cell transistor in a second direction perpendicular to the first direction; a first word line electrically connected to a gate of the first memory cell transistor; a first transistor having a channel region in the first active region, the first transistor configured to control supply of a voltage to the first memory cell transistor through the first contact and the first word line; a first bit line electrically connected to a drain of the first memory cell transistor; and a sense amplifier provided on the second substrate and electrically connected to the first bit line, the sense amplifier configured to control supply of a voltage from the sense amplifier to the drain of the first memory cell transistor through the first bit line, wherein the first substrate, the first memory cell transistor, the second memory cell transistor, the first word line, the first bit line, and the sense amplifier are provided in a first chip, and the second substrate and the first transistor are provided in a second chip. ### Claim 8 (depends on 7) The device of claim 7, further comprising: a first bonding electrode electrically connected to the first word line; and a second bonding electrode electrically connected to the first transistor, wherein the first bonding electrode and the second bonding electrode are directly bonded together. ### Claim 9 (depends on 7) The device of claim 7, further comprising: a capacitor provided adjacent to the first transistor in a second direction perpendicular to the first direction. ### Claim 10 (depends on 9) The device of claim 9, wherein the sense amplifier is disposed above the capacitor in the first direction. ### Claim 11 (depends on 7) The device of claim 7, further comprising: a third memory cell transistor; a second word line; a second contact; a second word line electrically connected to a gate of the third memory cell transistor through the second contact; and a second transistor having a channel region in the second active region, the second transistor configured to control supply of a voltage to the third memory cell transistor through the second contact and the second word line. ### Claim 12 A storage device comprising a first substrate having a first active region; a second substrate having a second active region, the second substrate provided above the first substrate in a first direction orthogonal to a surface of the first substrate; a first memory cell transistor provided between the first substrate and the second substrate in the first direction; a first word line electrically connected to a gate of the first memory cell transistor; a first bit line electrically connected to a drain of the first memory cell transistor; a first transistor having a channel region in the first active region, the first transistor configured to control supply of a voltage to the gate of the first memory cell transistor through the first word line; a sense amplifier having a channel region in the second active region, the sense amplifier configured to control supply of a voltage to the drain of the first memory cell transistor through the first bit line; and a capacitor provided adjacent to the first transistor in a second direction perpendicular to the first direction. ### Claim 13 (depends on 12) The storage device of claim 12, further comprising: a second memory cell transistor provided between the first substrate and the second substrate in the first direction; and a first contact provided between the first memory cell transistor and the second memory cell transistor in a second direction perpendicular to the first direction, wherein the first transistor is electrically connected to the gate of the first memory cell transistor through the first contact and the first word line. ### Claim 14 (depends on 12) The storage device of claim 12, further comprising: a second memory cell transistor provided between the first substrate and the second substrate in the first direction; a second word line electrically connected to a gate of the second memory cell transistor; and a second transistor having a channel region in the second active region, the second transistor configured to control supply of a voltage to the gate of the second memory cell transistor through the second word line. ### Claim 15 (depends on 14) The storage device of claim 14, further comprising: a first contact provided between the first memory cell transistor and the second memory cell transistor in a second direction perpendicular to the first direction; and a second contact provided between the first memory cell transistor and the second memory cell transistor in the second direction, wherein the first transistor is electrically connected to the gate of the first memory cell transistor through the first contact and the first word line, and the second transistor is electrically connected to the gate of the second memory cell transistor through the second contact and the second word line. ### Claim 16 (depends on 12) The storage device of claim 12, wherein the sense amplifier is disposed above the capacitor in the first direction.