# US 12,183,400 B2 · Three dimensional stacked nonvolatile semiconductor memory having a controller configured to execute a program operation on memory cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,400 B2 - Document ID: US12183400B2 - Status: Granted - Kind: B2 - Application number: 18/340,977 - Filed: 2023-06-26 - Published: 2024-01-04 - Granted: 2024-12-31 - Earliest claimed: 2008-04-23 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hiroshi Maejima - Web page: https://patentgrep.com/patent/US12183400B2 ## CPC - G11C 16/10: Programming or data input circuits - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 16/04: using variable threshold transistors, e.g. FAMOS - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 16/3422: {Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block. ## Claims ### Claim 1 A memory device comprising: a memory string including a first select transistor, a second select transistor, and a plurality of memory cells electrically coupled between the first select transistor and the second select transistor in series; and a controller coupled to the memory string, the controller configured to execute a program operation on one of the plurality of memory cells by: applying, during a first time period, a first voltage to gates of the plurality of memory cells, applying, during the first time period, a second voltage higher than the first voltage to a gate of the first select transistor, applying, during a second time period after the first time period, a third voltage higher than the first voltage to a gate of the one of the plurality of memory cells, and applying, during the second time period, a fourth voltage lower than the second voltage to the gate of the first select transistor. ### Claim 2 (depends on 1) The memory device of claim 1, further comprising: a source layer coupled to the first select transistor. ### Claim 3 (depends on 2) The memory device of claim 2, further comprising: a bit line coupled to the second select transistor. ### Claim 4 (depends on 2) The memory device of claim 2, wherein the controller is configured to apply, during the first time period, a fifth voltage lower than the second voltage to a gate of the second select transistor. ### Claim 5 (depends on 4) The memory device of claim 4, wherein the controller is configured to apply, during a third time period between the first time period and the second time period, the second voltage to the gate of the second select transistor. ### Claim 6 (depends on 5) The memory device of claim 5, wherein the controller is configured to apply, during the third time period, a sixth voltage lower than second voltage to the gate of the first select transistor. ### Claim 7 (depends on 1) The memory device of claim 1, further comprising: a bit line coupled to the first select transistor. ### Claim 8 (depends on 7) The memory device of claim 7, further comprising: a source layer coupled to the second select transistor. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the controller is configured to apply, during the first time period, a fifth voltage lower than the second voltage to a gate of the second select transistor. ### Claim 10 (depends on 1) The memory device of claim 1, wherein the controller is configured to apply, during the second time period, a fifth voltage between the first voltage and the second voltage to gates of other memory cells of the plurality of memory cells excluding the one of the plurality of memory cells. ### Claim 11 (depends on 10) The memory device of claim 10, wherein the controller is configured to apply, during a third time period between the first time period and the second time period, the fifth voltage the gates of the plurality of memory cells. ### Claim 12 A method of executing a program operation on one of a plurality of memory cells of a memory string, the memory string including a first select transistor, a second select transistor, and the plurality of memory cells electrically coupled between the first select transistor and the second select transistor in series, the method comprising: applying, during a first time period, a first voltage to gates of the plurality of memory cells; applying, during the first time period, a second voltage higher than the first voltage to a gate of the first select transistor; applying, during a second time period after the first time period, a third voltage higher than the first voltage to a gate of the one of the plurality of memory cells; and applying, during the second time period, a fourth voltage lower than the second voltage to the gate of the first select transistor. ### Claim 13 (depends on 12) The method of claim 12, including, applying, during the second time period, a fifth voltage between the first voltage and the second voltage to gates of other memory cells of the plurality of memory cells excluding the one of the plurality of memory cells. ### Claim 14 (depends on 13) The method of claim 13, including, applying, during a third time period between the first time period and the second time period, the fifth voltage the gates of the plurality of memory cells.